一個基於路徑延遲慣量之新延遲障礙測試方法

Abstract

一個邏輯電路要正常工作，需要內部所有路徑傳遞的延遲時間都少於所設計的時脈週期。然而在製程中所產生的缺陷及參數隨機的變異，常常導致傳遞的延遲時間無法達到我們所需要的範圍內。一般使用的測試方法是在較慢或等速的測試頻率下，輸入隨機或固定的兩個向量的測試樣本，來偵測所製成的電路是否符合規格。在此論文中，吾人提出一個基於路徑延遲慣量的路徑延遲障礙的新測試方法。藉由找出通過一條路徑所需要的最小寬度的脈衝，我們發現其寬度和同一條路徑的延遲時間有極高的正相關性。利用此結果去模擬及偵測製程變動所產生的路徑延遲障礙，我們所提出的測試方法得到了一個相當高的偵測率。吾人亦提出了一個可以用在此測試方法的產生脈衝的電路架構。我們所需要的最小寬度的脈衝，可以經由自動或手動地精確的獲得。

Correct operation of a logic circuit requires propagation delays of all paths in the circuit to be smaller than the intended clock interval. Defects and/or random variations in process parameters often cause propagation delays to fall outside the desired limits. Random or deterministic two-vector tests, conducted at the slow or rated clocking rate, can be used to insure that path delays in manufactured circuits meet the specifications. In this thesis, we propose a new path delay fault test scheme based on the delay inertia of the path. The delay inertia of a path is the quantity of the energy which a pulse needs to contain in order to propagate through the path. Theoretical analysis shows that the delay inertia of a path is proportional to the propagation delay time in terms of the number of stages, the fanout, and the loading (i.e., the length) of the path. The simulation results on the proposed scheme considering process variations, which will cause the transistor parameter variations, show a high detection probability for detecting path delay faults for the scheme. A circuit has also been proposed to generate the pulse of the required pulse width. The circuit can be operated automatically or manually.