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dc.contributor.authorLiao, Chia-Chunen_US
dc.contributor.authorChiang, Tsung-Yuen_US
dc.contributor.authorLin, Min-Chenen_US
dc.contributor.authorChao, Tien-Shengen_US
dc.date.accessioned2014-12-08T15:07:06Z-
dc.date.available2014-12-08T15:07:06Z-
dc.date.issued2010-04-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2010.2041524en_US
dc.identifier.urihttp://hdl.handle.net/11536/5571-
dc.description.abstractIn this letter, we certify that the compressive SiN capping layer has more potential than the tensile layer for fabrication using the stress memorization technique to enhance NMOS mobility. The mechanism that we have proposed implies that the conventional choice of the capping layer should bemodulated from the point of view of stress shift rather than using the highest tensile film.en_US
dc.language.isoen_USen_US
dc.subjectContact etch-stop layer (CESL)en_US
dc.subjectpoly amorphization implantation (PAI)en_US
dc.subjectstrainen_US
dc.subjectstress memorization technique (SMT)en_US
dc.titleBenefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanismen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2010.2041524en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume31en_US
dc.citation.issue4en_US
dc.citation.spage281en_US
dc.citation.epage283en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.identifier.wosnumberWOS:000276017000008-
dc.citation.woscount7-
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