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dc.contributor.authorWeng, Wu-Teen_US
dc.contributor.authorLee, Yao-Jenen_US
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorHuang, Tiao-Yuanen_US
dc.date.accessioned2014-12-08T15:07:08Z-
dc.date.available2014-12-08T15:07:08Z-
dc.date.issued2010-04-01en_US
dc.identifier.issn0038-1101en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.sse.2010.01.007en_US
dc.identifier.urihttp://hdl.handle.net/11536/5606-
dc.description.abstractThis study examines the effects of plasma-induced damage (PID) both on advanced SiO(2)/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO(2)/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology. (C) 2010 Elsevier Ltd. All rights reserved.en_US
dc.language.isoen_USen_US
dc.titleA comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO(2)/poly-gate complementary metal oxide semiconductor technologyen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/j.sse.2010.01.007en_US
dc.identifier.journalSOLID-STATE ELECTRONICSen_US
dc.citation.volume54en_US
dc.citation.issue4en_US
dc.citation.spage368en_US
dc.citation.epage377en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
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