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dc.contributor.authorLiu, Tsu-Mingen_US
dc.contributor.authorLin, Ting-Anen_US
dc.contributor.authorWang, Sheng-Zenen_US
dc.contributor.authorLee, Wen-Pingen_US
dc.contributor.authorYang, Jiun-Yanen_US
dc.contributor.authorHou, Kang-Chengen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2014-12-08T15:07:09Z-
dc.date.available2014-12-08T15:07:09Z-
dc.date.issued2007-01-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://dx.doi.org/10.1109/JSSC.2006.886542en_US
dc.identifier.urihttp://hdl.handle.net/11536/5613-
dc.description.abstractA low-power dual-standard video decoder has been developed for mobile applications. It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a single chip and features a scalable architecture to reach area/power efficiency. This chip integrates diverse algorithms of MPEG-2 and H.264/AVC to reduce silicon area. Three low-power techniques are proposed. First, a domain-pipelined scalability (DPS) technique is used to optimize the pipelined structure according to the number of processing cycles. Second, bandwidth scalability is implemented via a line-pixel-lookahead (LPL) scheme to improve the external bandwidth and reduce the internal memory size, leading to 51% of memory power reduction compared to a conventional design. Third, low-power motion compensation and deblocking filter are designed to reduce the operating frequency without degrading system performance. A test chip is fabricated in a 0.18 mu m one-poly six=metal CMOS technology with an area of 15.21 mm(2). For mobile applications, H.264/AVC and MPEG-2 video decoding of quarter-common intermediate format (QCIF) sequences at 15 frames per second are achieved at 1.15 MHz clock frequency with power dissipation of 125 mu W and 108 mu W, respectively, at 1 V supply voltage.en_US
dc.language.isoen_USen_US
dc.subjectH.264/AVCen_US
dc.subjectinverse discrete cosine transform (IDCT)en_US
dc.subjectmobile communicationen_US
dc.subjectmotion compensationen_US
dc.subjectMPEG-2en_US
dc.subjectvideo codingen_US
dc.titleA 125 mu W, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applicationsen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1109/JSSC.2006.886542en_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume42en_US
dc.citation.issue1en_US
dc.citation.spage161en_US
dc.citation.epage169en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000243287500018-
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