應用於數位電視之視訊雙標準解碼器設計與實現

Abstract

H.264/AVC是最新一代的視訊壓縮標準，比起MPEG-2，H.261及H.263，H.264提供了更高的壓縮效能，在相同的壓縮比率下提供更好的影像品質。在本論文中，我們實作了一個H.264的硬體影像解碼器。我們運用各樣的技術及架構，來提高單位時間資料流通量以及降低功率的消耗，以期達到未來不論在數位電視、無線傳輸等方面的影像解碼需求。此外，因為多標準解碼器已成為設計潮流，我們把目前最流行且運用在DVD的影像標準規格—MPEG-2也納入我們的設計範圍。我們期望運用硬體共用的技巧，在不花費太多額外的硬體架構下，用現有的硬體單來實現MPEG-2的硬體解碼功能。 從系統設計的角度，在這篇論文我們首先提出了一個雙標準的影像解碼區塊圖，說明我們共用了那些硬體單元，及主要資料的流動路徑。我們採用了複合式4乘4 區塊管線化系統架構來減少區間暫存器的使用量並加速系統的單位時間資料流通量。我們提出的有效率解碼順序也能減少在移動補償及空間預測模組之記憶體存取次數。在解碼的資料流動路徑中，剩餘像素及預測像素值的相加處發生的資料同步問題我們並提出了一個可變長度先進先出緩充暫存器的解決方案。我們也提出了一個利用CBP參數來節省功率的方法。 在模組架構設計方面，我們也針對此解碼器的各模組做了介紹。在資料流分析單元，我們採用階層化的設計方式，不但架構簡單易於設計，也可以有效降低功率消耗。暫存器共用的技巧也被應用於資料流分析單元，而達到共用暫存器的目的。在空間預測模組的設計中，我們提出了三種並行的暫存器架構以幫助空間預測的運算，記憶體存取次數也可以因此減少到最低。其餘模組的設計也包含在這個論文中，許多的技巧也被應用在節省記憶體存取次數及加快單位時間資料流通率。 最後本論文利用UMC 0.18um 1P6M製程技術實作了這顆H.264/MPEG-2雙模式影像解碼晶片。根據合成與佈局繞線結果，這顆晶片的大小為3.9×3.9mm2，總邏輯閘數為491K，最大操作頻率可達83.3MHz。支援即時播放720pHD的H.264影像串流於56MHz，720pHD的MPEG-2影像串流於35.7MHz在每秒30張的規格下。

H.264/AVC is the newest video coding standard. Compared with MPEG-2, H.261, and H.263, H.264 provides better coding efficiency, which means that it provides better image quality at the same coding rate. In this thesis, we implemented an H.264 video decoder. We adopted various techniques and architectures to accelerate the decoding throughput and the reduction on power consumption, to achieve the demands on future digital TV and wireless communication. Besides, because the multi-mode video decoder is a design trend, the video coding standard – MPEG-2 which has been widely used for DVD video standard is included in our design. We expect to use some hardware-sharing techniques to implement the MPEG-2 video decoder in the situation that only a few additional hardware modules are required. From the system point of view, in this thesis we first proposed a block diagram for dual mode video decoder, to illustrate the functional blocks we used, and the data path of our work. The efficient decoding ordering we proposed can reduces the memory access times on motion compensation and intra prediction modules. In the decoding loop, the synchronization problem occurs at the adder that adds the residual pixel values with the predicted pixel values. We proposed a variable-length FIFO architecture for the solution to this synchronization problem. We also proposed a way to save power by exploiting the system parameter “coded-block-pattern”. In the architecture design, we give descriptions on all the important modules of this decoder. We adopt a hierarchical structure for the syntax parser design. Hierarchical structure make the parser easy design, the clock-gating power reduction technique can also be effectively applied to save power in this structure. The register sharing technique is also applied in the syntax parser unit in order to reduce the amount of register required. In intra predictor design, we proposed three kinds of buffers to reduce the design complexity on intra predictor. The memory access times can be reduced to minimum for the help of these 3 buffers. Besides, other important modules like motion compensation, de-blocking filters are also included in this thesis. Many techniques are also applied to save memory access times and to increase the throughput in these modules. At last we implemented this dual mode H.264/MPEG-2 video decoder in UMC 0.18um 1P6M process. According to the implementation result, the size of his chip is 3.7×3.7 mm2, total gate count is 491K, and the maximum working frequency is 83.3MHz. This chip supports real time decoding 720pHD H.264 video sequence in 56MHz, 720pHD MPEG-2 video sequence in 35.7MHz in 30fps.