資料驅動之混合架構的效能評估

Abstract

近來，結合 dataflow 與傳統 von Neumann 執行模式的設計，是發展高 效能處理機的一個新趨向。本篇論文即針對一種新的資料驅動之混合式計 算機架構，提出分析模型以進行其執行效益的評估。同時經由另外建立的 架構模擬模型，對前面的分析模式來直接加以驗證其正確與否。此新提出 的處理機構造與 MIT 發展的 Monsoon 架構有相似之處，即兩者皆同屬於 具資料驅動能力的管線處理器 (data-driven pipelined processor) 。 然而，新架構與 Monsoon 不同的地方在於：新架構總是處理 enabled指 令，而 Monsoon 卻不盡如此。但是在新架構中，會有二個指令同時要求 取用記億體的情形：一者需作運算元之收集，另一指令則要將已完成運算 之結果存入記億體。因此，記億體模組應該要能同時允許二至四個記億體 讀寫的能力。如果記億體模組沒有適當的設計，則可能會因而形成整個系 統的瓶頸所在。鑑於此，我們對各種不同的記億體組態來作效率評量；這 些不同的組態包括不同的記億體交錯程度 (degree of memory inter- leaving) ，以及調整 write buffer 的容量。最終評估的結果証實此一 新架構，在 memory interleaving 的程度很小和 write buffer 的數量 很少的情況下，便已能達到非常高的功率。 The combination of dataflow and von Neumann execution models is a recent trend in designing high speed processors. In this thesis, an analytical model of a novel data-driven hybrid computer architecture is presented and a simulation of the arch- itecture is also conducted to verify the correctness of the ana- lytical model. Similar to the Monsoon architecture developed at MIT, the underline of the presented architecture is a data-driven pipelined processor. However, it differs from the Monsoon archi- tecture in the sense that only enabled instructions can enter the pipeline. Nevertheless, as noted in the thesis, there could be two instructions which issue memory accesses simultaneously in the pipe of the proposed architecture: one instruction assem- bling its operands and another writing its results. Therefore, the memory system must be able to support two to four simultan- eous memory accesses in one pipeline cycle. Clearly, the memory system would be the bottleneck of the architecture if it is not designed properly. Hence, the analytical model is constructed based on various configurations of the memory system: various degrees of memory interleaving and different numbers of write buffers. The evaluation results show that the proposed architec- ture can easily achieve high performance with small degree of interleaving as well as number of write buffers.