用於次頻編碼之超大型積體電路設計

Abstract

近來在視訊編碼的標準制訂上已有許多進展，移動補償 (motion compensation) 配合離散餘弦轉換(DCT) 是眾多標準所採用的編碼方法。 這是一種高效率的編碼方法，但是應用在低位元傳輸率的系統中，則會產 生區塊效應(block effect)而降低影像品質。次頻編碼 (subband coding) 使用另一種分頻方式，以此方法編碼之影像不會有區塊效應的缺 點。次頻編碼器包括兩大部分，一部分是濾波元件組，另一部分是編碼與 解碼器。最常使用的樹狀濾波元件組是由有限脈衝響應濾波器所架構的。 一個即時濾波元件組的單位時間計算量甚巨，因此在本論文中便提出高速 有限脈衝響應濾波器晶片之設計，此晶片採用管線式架構，每秒可作11.2 億個乘法與加法運算，使其足以作為次頻編碼器之核心處理器。 A great deal of progress has been made recently in the standardization of video coding algorithms both for telecommunications and multimedia applications. The basis of these standards is the motion compensated discrete cosine transform (MC-DCT). Although these algorithms are efficient to implement due to their local operations and small memory requirement, their performance at low bit rates is limited by motion compensation and DCT block artifacts. Subband coding provides an alternative frequency domain representation which decomposes the image sequence into frequency bands without introducing spatial block effects. A subband coder contains two main parts, one is the analysis/synthesis filter banks and another is the subband signal encoder/decoder. The most widely used M-band filter banks are designed with FIR filters organized in a hierarchical structure. To implement a real-time filter bank, a powerful computational component is needed. In this thesis, a 16-tap FIR filter with on chip video line delays was proposed. The chip is fully pipelined and has a throughput rate of 70 MHz. It performs 1.12 billion (12*9)-bit multiplications, 1.12 billion 25-bit additions per second in less than 1 cm by 1 cm of silicon area. By using the FIR chip as the core processor, a real-time filter bank for subband coding can be constructed.