短通道埋層n-MOS場效電晶體之計算機模擬

Abstract

本文由埋層n-型金氧半場效電晶體的基本元件物理推導出臨界電壓和電流 －電壓之解析模式。根據這些模式，本文提出一套有系統的元件參數萃取 方法來萃取元件結構與材料參數。元件結構參數包括等效通道長度､通道 雜質分佈､汲╱源極雜質分佈及接面深度。材料參數包括移動率模式的參 數。利用這些萃取的參數，我們可以使用一個二維金氧半電晶體模擬器來 模擬實驗測試鍵的電氣特性，並顯示測試鍵中不同通道長度及工作於各種 不同偏壓狀態下的模擬結果和所測量元件的特性非常地吻合。利用模擬的 方法，本文探討短通道埋層n-型金氧半場效電晶體的抵穿效應和汲極引起 的電位障壁降低，並提出改善抵穿效應的方法。 In this thesis, the basic device physics of a buried chan- nel n-MOSFET are described, which include the threshold-volta- ge model and I-V characteristics. Based on these models, the extraction methods for the device parameters including the de- vice structure parameters and the material parameters are pre- sented. The device structure parameters include effective cha- nnel length, channel doping profile, and source/drain doping profile and its junction depth. The material parameters inclu- de the parameters in the mobility model. Using these extracted parameters, we can simulate the electrical characteristics of the fabricated buried channel n-MOSFET's by using a two-dimen- sional numerical MOSFET simulator ( SUMMOS ). It is shown that good agreements between simulation results and experimental data are obtained for wide ranges of applied biases and chann- el lengths. Based on the simulation, the drain-induced barrier loweri- ng and punch-through effects of short-buried-channel n-MOS- FET's are discussed, and the methods for improving these short-channel effects are proposed.