DS-BPSK 展頻傳輸系統之架構設計

Abstract

隨著個人無線通訊的應用日益增加，展頻通訊的技術愈來愈受到重視．因 為它的一項應用－分碼傳輸(CDMA)可以較傳統的分頻(FDMA)或分時( (TDMA)傳輸方法在相同的頻寬下容納更多的使用者．由於超大型積體電路 技術一日千里，將一件通訊產品的大部分甚或全部的元件整合在同一塊晶 片的理想不再遙不可及．在本論文中，我們提出一個可使用目前數位積體 電路技術來實現的展頻通訊傳收器的架構．這個架構的特色包括 1.使用 Gold code 方法所設計的一個 pseudo-noise 產生器．2.用數位 Costas loop 來作載波同步．3.用連續搜尋的方法來作展頻碼的同步．我們用電 腦模擬來評估該架構的好壞，發現它具有容易製作及快速同步的好處．但 也發現它的性能並不如想像中的好．在本論文最後，我們將討論這些優缺 點的原因並提出未來可能的研究方向． With the tremendous growing demand in personal communica- tion, the spread spectrum technique is drawing much attention gradually. In this thesis, we focused on the design of a Di- rect Sequence-Binary Phase Shift Keying(DS-BPSK) spread spec- rum transceiver. A digital VLSI architecture to implement the transceiver was proposed. Various design aspects of the arc- hitecture including Gold code structured pseudo-noise genera- tor, digital Costas loop, and serial search acquisition meth- od were carefully studied and simulated. Overall performance of the design was evaluated through the full simulation. We found that the advantages of our architecture includes easy implementation and fast acquisition. However, the performance was not as good as we wish. The reasons were explored and some future works were presented in the final part of this thesis.