超大型積體電路類比數位混合式模擬器之設計

Abstract

混合式模擬器是目前類比數位式超大型積體電路時序驗證工具之一。我們 利用事件趨動的觀念，發展了一個混合式的模擬器，它結合傳統電路的模 擬技術，取樣資料電路技術來模擬類比電路以及閘電路的數位電路模擬技 術。為了節省記憶體的儲存量及花費較少的執行時間且同時還保有合理的 準確性，一個新的微細胞元（ Macrocell）的設計方法被提出來。它將一 個電路分解成許多子電路，稱微細胞元。這個方法能開發出一個廣義的多 重速率（ multirate）行為，亦即微細胞元的模擬，是在不同速率下進行 。因此，此一混合式模擬器可以對不同性質的電路使用不同的演譯法（ algorithm）。尤有進者，我們提出一新的分割方法，其中，它包含時間 的分割與微細胞元的分割。因為這些被分解的塊狀（ Block）成管線流（ Pipeline）的架構，因此它能進一步地在多微處理器的機器上執行來提高 速度。我們執行了幾個例子做速度與準確性測試，結果證實本模擬器的性 能優越。這混合式模擬器相當合適於以細胞元為基本的階層式（Hiera rchical）超大型積體電路，如目前特殊功能積體電路的設計。 The mixed-mode simulator is currently one of the most efficit tools for timing verification of analog-digital CMOS VLSI circuits. We have developed a mixed-mode simulator by combining the conventional circuit level simulation techniques, sampled- data level circuit techniques for analog circuit simulation and the gate level techniques for digital circuit simulation based on the event-driven concept. A new scheme at the macrocell level is proposed for memory storage savings and less execution time required while preserving reasonable accuracy. It decomposes a circuit into a number of subcircuits called macrocells. The scheme can exploit a general multirate behavior that refers to macrocell simulation at different rates over a given interval of time so that different algorithms can be employed in the simulator. Furthermore, a new partitioning scheme called block tearing approach is proposed, in which timing partition is used in addition to the partition of macrocells. It can further be implemented in multi-processor machines to speed up since these partitioned blocks are built upon the pipeline structure. Benchmark tests of several example circuits show good performance in terms of speed and accuracy. The simulator is well suited for hierarchical VLSI circuits which are cell- based such as current circuit design.