VSELP語音編碼器之特殊數位信號處理器架構

Abstract

在此論文中,我們試圖完成一8Kbps之語音編碼/解碼器. 雖然此編碼方式 可利用坊間的一般用途數位信號處理器(DSP)來完成,但我們係為了低功 率,整體實作大小及成本之考量,來進行特殊功能積體電路(ASIC)之設計. 以下的論文中,我們將敘述VSELP的演算法(algorithm). 我們也將描述此 特殊數位信號處理器之指令集(Instruction Set)及系統架構,同時也包含 針對VSELP所寫程式之模擬結果. The main topic for this thesis is our implementation of an 8Kbps Vector Sum-Excited Linear Prediction (VSELP) speech CODEC (encoder and decoder). Meanwhile, we intent to implement it as a low-power-consumption ASIC instead of utilizing the existing general purpose DSP chips. We are also going to describe the VSELP algorithm and the custom processor architecture which we developed. Furthermore, we will describe the instruction set of this processor and the simulation result of this architecture with assembly codes for VSELP is also included.