以內容地址記憶器架構且基於單ㄧ事件等效的序向障礙模擬

Abstract

本篇論文中,我們結合內容地址記憶器的特性和單ㄧ事件等效的優點來處 理零延遲的閘級同步序向電路障礙模擬。內容地址記憶器的模擬方法可以 將內容地址記憶器當成平行處理機器,能將多個障礙模擬ㄧ次處理。如此 可以減少所耗費的時間;而加入單ㄧ事件等效的觀念,可以摺疊障礙來降低 障礙的次數,而且可減少內容地址記憶器的大小。我們利用以上兩種方法 追求降低內容地址記憶器的大小到合理的範圍中,並可得到較好的大小和 時間之倍數比。 In this thesis, we propos a content addressable memory architecture to do the zero delay fault simulation of gate level synchronous sequential circuit based on the single event equivalence. The use of the content addressable memory architecture attempts to reduce the computation time by processing many faults at a time. Incorporating the single event equivalence can reduce the number of faults and the size of content addressable memory by collapsing faults dynamically. Combination of the above two approaches reduces the size of content addressable memory to a reasonable size while gains better ratios of the size and the processing time.