用於視訊處理的資料列序器

Abstract

本論文提出一個適用於視訊處理的資料列序器。它的功能主要是對影像中 的資料作重新排列。這個以記憶體為基本架構的資料列序器不同於以暫存 器為基本架構的資料列序器，它最大的優點是擁有強大的可程式性。這可 程式性是來自於可產生記憶體存取位址的多功能位址產生器。這個位址產 生器包括了線性掃描，區塊掃描，反區塊掃描，鋸齒狀掃描，反位元流掃 描，蝶式掃描，可變區塊大小，以及重疊區塊掃描等各種功能。結合了記 憶體，位址產生器，以及佇列，我們設計了一個可補償列序器兩端速度差 異，而以記憶體為基本架構的可程式性資料列序器。除此之外，我們也設 計了一個適用於視訊處理的記憶體組織。這個記憶體組織使用了多模組的 記憶體來代替多埠記憶體以避免使用多埠記憶體的巨大硬體面積，並提供 了足夠的記憶體頻寬。 In this thesis, a data sequencer suitable for video signal processing is proposed. The primary function of the data sequencer is to consider the reordering of image pixels. The proposed data sequencer is based on memory. This is different from a register-based one. Compared with a register-based sequencer, the major advantage of the memory-based one is its vital programmability. This programmability comes from the multi-functional address generators that generate the addresses for the memory access. The functions of the proposed data sequencer include raster-scanning, block-scanning, transpose- scanning, zigzag-scanning, bit-reverse sequence, butterfly sequence, multiple-blocksize, and block overlapping. Combining the address generators, memory, and FIFOs, we can obtain a memory-based programmable data sequencer which can compensate the discrepancy in speed at both ends of the sequencer. Besides, a memory organization for the VSP processors together with its address generation are also proposed. This memory organization is able to avoid the area penalty of the multi- port memory, and it uses the multiple-bank memory to provide sufficient memory bandwidth.