應用於訊號處理之位址產生器

Abstract

由於半導體科技的進步, 大量的運算處理功能可以被置於一個訊號處理晶 片中, 因此，速度的提昇便轉而受限於資料的存取。研究位址產生器的動 機便起源於如何突破此限制。在本篇論文中，我們發展了一套合成工具， 可以有效的合成一個位址產生器。使用者只須寫一段行為描述來指出位址 產生的順序，以這段描述當成合成工具的輸入， 然後這合成工具便能產 生一個以 Verilog 格式表示之線路。這線路中包含計數器以及一些邏輯 閘，它們均是以模組的形式顯現於線路中。試驗結果證明，輸出線路能滿 足規格的要求，而且僅佔用了少量的晶片面積。由此可知這個工具提供了 一套有效的方法來提昇訊號處理晶片之功能。 Though advanced technology allows to put large computation power on a signal processor chip, the accessing ability of a signal processor may become another limitation on its performance. This is the motivation to study efficient address generation method. In this thesis, we develop a useful and efficient synthesis tool, SAG (Synthesizer for Address Generation), for automatic construction of the address generator. The only thing which user should do is to write a behavior description for the desired address sequence. With the behavior description as input, the synthesizer SAG will construct the address generation circuit in the form of Verilog net-list as Output. This net-list consists of counters and combinational logics and represented in the form of modules. Test results show that the output net-lists satisfy the specifications and occupy very small chip area. Thus this SAG synthesizer provide an efficient way to design address generation for performance improvement of signal processing chips.