同步化單對線數位用戶迴路接收端之初始化時脈

Abstract

本文主要藉由G994.1所規範的握持程序探討SHDSL時脈恢復工作，G994.1主要彈性地對各個不同xDSL的傳接器在初始化的程序統一規範。由於SHDSL使用單對銅線傳輸其載波頻率為單一頻率，為了實現此一傳輸協定之時脈恢復工作，我們提出以非線性產生光譜線無資料輔助的方式來作為同步化設計依據，設計的方式以純數位化的方式不需額外的控制電路調整真實時脈的取樣速度，我們所提出時脈復原的架構其中包含交織插補濾波器來做數位化重新取樣運算、前置濾波器過濾雜訊及降低取樣輸出速度、時脈誤差偵測器計算時脈誤差資訊、鎖相迴路抑制收斂時脈誤差的偏移。當完成時脈復原工作後，最後便是將G994.1傳輸資訊的內容解碼譯出成原始資料。 接收端於初始啟動階段要做時脈復原、等化器、迴響消除、相聲穿越等工作，主要分成前置啟動部份與啟動部份兩段，前置啟動部份主要藉由G994.1握持程序將系統的時脈粗調與相關的補償工作，此期間除需完成補償工作外時脈誤差必須在±50 ppm以內，到啟動部份進入資料模式必須將時脈鎖住到更小誤差範圍，此誤差範圍與補償工作影響重大，本文實際以C語言模擬定點實現方式，在完全不做任何補償工作的情況下，成功在前置啟動階段即完成時脈恢復工作達±50ppm誤差要求範圍內，若是要進一步改善時脈同步化的精確度可增加各端輸出位元，而時脈偏移率將可達到約±10ppm ，此一結果將有助於接收器分配更多的時間專注於調整補償工作。

We will confer the timing recovery of the SHDSL by the Recommendation G994.1 handshake procedure. This Recommendation provides a flexible mechanism for various Digital Subscriber Line (DSL) transceivers at the start-up procedure. SHDSL technology was available over a single pair copper line with single tone carrier frequency, for the implement of the timing recovery by the Recommendation, we provide architecture that base on the Non-linear Spectral Line method and non-data aided with all-digital way without additional control circuit adjusting the real clock timing. Including of Digital Interpolator for digitally resampling, Prefilter for filtering noise and downing the throughput, Timing Error Detector for computing the timing error information, Phase Lock Loop for the convergence of timing error offset. After achieving timing recovery, we will decode and recover G994.1 transmitting data. Timing recovery, equalizer, echo canceller, crosstalk…etc are needed at the start-up procedure of the receiver. There are two major parts that are pre-activation and activation part. In the pre-activation part, the system of the timing clock should have coarse adjustment by the G994.1 procedure and fine compensations. During the period, not only the compensations will be well operated but the clock offset shall be within ±50ppm. After entering activation procedure and data mode, the clock offset should be locked in a small error range more. The compensation works will be deeply impact on the error range. In this thesis, the fixed-point implement was simulated on C language. Without doing any compensation, we successfully recover the timing error with the demand for ±50ppm clock offset range at the pre-activation process. With using more bits on each stage of the output, we can promote the accuracy of the clock and reduce its offset range to ±10ppm. The result will help receiver to have more time to do other compensation works.