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dc.contributor.authorHuang, Po-Chunen_US
dc.contributor.authorChen, Lu-Anen_US
dc.contributor.authorSheu, Jeng-Tzongen_US
dc.date.accessioned2014-12-08T15:07:20Z-
dc.date.available2014-12-08T15:07:20Z-
dc.date.issued2010-03-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2009.2038177en_US
dc.identifier.urihttp://hdl.handle.net/11536/5777-
dc.description.abstractA high-performance gate-all-around (GAA) poly-Si nanowire (NW) SONOS-type memory thin-film transistor (TFT) is presented. The presence of the corners of the GAA structure resulted in the program speed and memory window of this device being superior to those of a planar poly-Si TFT device. When erasing, planar devices exhibit a threshold-voltage shift resulting from gate injection; the GAA device was immune to this behavior. The presence of a nonuniform electric field in the channel region during programming and erasing was confirmed through simulation. The device also exhibited superior endurance and data-retention behavior.en_US
dc.language.isoen_USen_US
dc.subjectField enhancementen_US
dc.subjectgate-all-around (GAA)en_US
dc.subjectgate injectionen_US
dc.subjectnanowire (NW)en_US
dc.subjectSONOSen_US
dc.subjectthin-film transistor (TFT)en_US
dc.titleElectric-Field Enhancement of a Gate-All-Around Nanowire Thin-Film Transistor Memoryen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2009.2038177en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume31en_US
dc.citation.issue3en_US
dc.citation.spage216en_US
dc.citation.epage218en_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.department材料科學與工程學系奈米科技碩博班zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.contributor.departmentGraduate Program of Nanotechnology , Department of Materials Science and Engineeringen_US
dc.identifier.wosnumberWOS:000274995300013-
dc.citation.woscount19-
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