在分散式記憶體多處理器系統上智慧型繞徑器之設計

Abstract

藉著連接大量的低成本處理機，分散式記憶體多處理器提供了一個有效的 方法來達到超量運算(supercomputing)的要求。在這些分散式記憶體多處 理器上執行運算的程式彼此依靠訊息的傳遞互相溝通，藉以達到同步 (synchronization) 以及資料共享的目的。很不幸的，目前的處理機少有 提供訊息傳遞的機制，因而導致訊息傳遞時的啟動延遲(start-up delay) 支配了整個通訊上所花的時間。不僅如此，在一個多次傳遞架構(multi- hop topology)的多處理器系統中，整個訊息行進路線上的中間處理機必 須花費額外的時間來安排訊息的發送，進而影響了原本處理機的正常運算 工作。在本計劃中，我們設計了一個以硬體構成的智慧型繞徑器，用以降 低在訊息傳遞上的啟動延遲(start-up delay)以及去除中間處理機必須花 費在訊息處理上的負擔。除此之外，我們提出的處理機╱繞徑器介面允許 這個訊息繞徑器在分散式記憶體多處理器的系統中能夠適用於不同種類的 處理機，更增強了它的應用彈性。這個智慧型訊息繞徑器主要在 Verilog-XL 的環境下設計以及進行模擬。模擬的結果顯示它能夠有效地 降低處理機在傳遞訊息時的啟動延遲 (start-up delay)，同時我們也展 示了在整個訊息行進路線上的中間處理機如何使用這個訊息繞徑器來避免 正常運算工作被訊息傳遞所干擾。 Distributed memory multicomputers have recently offered an effective approach to supercomputing by connecting a large number of low-cost processors. Processes running on these processors of distributed memory multicomputers communicate with each other through message passing to achieve the goals of synchonization and data sharing. Unfortunately, few of the contemporary processors support message transmission mechanisms, thus, the start-up delay dominates the communication latency. Moreover, in a multi-hop topology multicomputer system, the routing processes also severely affect the normal computation jobs of the intermediate processors along the routing path. In this project, we design a hardware intelligent message router which can be used to reduce the message transmission start-up delay and off-load the burden of the processors from the normal computation. Besides, the proposed processor/router interface enables this message router to accommodate to heterogeneous processors in the distributed memory multicomputer system. This intelligent message router is implemented and simulated under the environment of Verilog-XL. The simulation result shows that the message router significantly reduces the start-up delay. And we also show how to prevent the intermediate processors from being interfered by using this intelligent message router.