非同步多核心處理器之訊息傳遞閉鎖機制設計

Abstract

近年來，由於單核心處理器的效能成長已趨近極限，多核心處理器架構與平行運算開始成為主流。一旦處理器的核心數變多，系統資源(如記憶體、輸入輸出等)的使用核心從只有一個變成多個，就必須有能確保資源使用時互斥的機制，以防止資源同時被多個核心存取而造成錯誤，此即所謂的鎖，而使用訊息傳遞的鎖又較使用共享記憶體的鎖更有可擴充性。現今的多核心處理器系統多使用晶片內網路連結各個核心及資源，因此可支援訊息傳遞，另因非同步系統比起需要時脈的同步系統更能節省功耗，因此本篇論文以一非同步雙道超大指令字組多核心處理器為基礎，修改其指令集架構，並於其上的晶片內網路加入一個鎖管理單元。我們將這個鎖管理單元以ModelSim 6.0模擬及驗證，使用TSMC 0.13微米的元件資料庫以Synopsys Design Compiler來做合成。

In recent years, because the performance growth of single chip processor has reached limit, multi-core processor architecture and parallel computing starts to become mainstream. Once the number of cores in a processor grows, the number of user of system resources(such as memory、I/O…etc) grows from only one to become more. In order to prevent errors caused by simultaneous accesses to a single resource from multi-core, a mutual exclusion mechanism of resource usage must be ensured, which is so-called lock. Using message-passing is more scalable than using shared-memory for lock design. Network-On-Chip is used to link processor-cores and resources in modern multi-core processor systems, so message-passing is supported. And asynchronous systems are more power-saving than clocked synchronous systems, so in this study, we modify the instruction set architecture based on a asynchronous two-way VLIW multi-core processor and add a lock management unit into its network. Functionality is simulated and verified by using ModelSim 6.0, and is synthesized with Synopsys Design Compiler using TSMC 0.13μm process library.