非同步雙道超大指令字組多核心處理器之資料路徑設計

Abstract

過去數十年，計算機架構設計都著力於追求高時脈，但現在時脈已經發展到一定的階段。在近這年來，處理器的發展已經由高時脈進入平行處理發展階段。到目前為止處理器的設計方向轉向多核心處理器發展，試圖以多核心處理器的技術來取代高時脈，而達到效能提升的目的，但時脈造成的耗電與熱能皆無法有效避免。 在1940年代開始，計算機架構的設計方式為了避免很多在非同步電路系統中可能衍生的問題而選擇了有clock的設計方式，因此現今大部分處理器都以同步系統為基礎而持續發展中。處理器在非同步系統的發展也有持續研究與成果展現，如：由英國曼徹斯特大學(University of Manchester)發表的AMULET系列微處理器。因此本篇論文以非同步系統為基礎，配合網路作為連結，實作出一個四核心超長指令字組非同步處理器。最後我們將這個四核心超長指令字組非同步多核心處理器以Synopsys Design Compiler來做合成，使用的是TSMC 0.13微米的元件資料庫並且以ModelSim 6.0模擬及驗證設計的正確性。

In the past few decades, frequency scaling of computer architecture has been a dominant reason for performance improvement. The developments of computer architecture have transferred from high frequency to parallelism handler technique in recent years. Computer systems need high computing power multimedia integration and reliable communication functionality single-core processor may not satisfy these requirements nowadays. In order to consume extra transistors, the computer architecture shifts to multicore architecture. Since more consumption of high power and heat energy that caused by clock distribution, the current trend of processors goes towards multicore processor. Most modern processors are based on synchronous circuit design nowadays. However, the clock distribution may cause serious problems in complex systems. In this study, we designed an asynchronous two-way VLIW multicore processor via interconnection network. At the end, the correct of function is verified by ModelSim 6.0 and synthesized by TSMC .13μm process library.