非同步雙道超大指令字組處理器之資料路徑設計

Abstract

過去數十年來，計算機架構發展快速，然而因為過去技術上的困難，在1940年代開始計算機架構的設計方式為了避免很多在非同步電路系統中可能衍生的問題而選擇了有clock的設計方式，因此現今大部分處理器都以同步系統為基礎而持續發展中。 然而這幾年來，處理器的發展已經由高時脈進入平行處理發展階段。到目前為止處理器的設計方向轉向多核心處理器發展，試圖以多核心處理器的技術來取代高時脈以達到效能提升的目的，而時脈造成的耗電與熱能皆無法有效避免。而處理器在非同步系統的發展也有持續研究與成果展現，如：由英國曼徹斯特大學(University of Manchester)發表的AMULET系列微處理器。因此本篇論文嘗試以非同步系統為基礎實作出一個架構簡單、適合建構成多核心處理器的超長指令字組非同步核心，期望未來把多個輕量化非同步核心以interconnection network作連結變成一個多核心非同步處理器。最後我們將這個超長指令字組非同步核心以Synopsys Design Compiler來做合成，使用的是TSMC 0.13微米的元件資料庫並且以ModelSim 6.0模擬及驗證設計的正確性。

Most modern processors are based on synchronous circuit design nowadays. The current trend of processors is towards multiprocessor because the higher power consumption and heat energy caused by clock distribution. Moreover, embedded multimedia system and Digital Signal Processor are more and more popular in recent years. DSPs are developed for handling a large number of image data. They improve performance with VLIW and SIMD in some instances. However, they are all based on synchronous circuit design. The clock distribution may cause a serious problem in complex systems. In this study, we try to design a light-weight core based on asynchronous circuit design. It is an asynchronous two-way VLIW processor and includes some special instructions for SIMD application. In the future, we can develop an asynchronous multi-core processor which is made up of this asynchronous two-way VLIW processor via interconnection network. Finally, the correct of function is verified by ModelSim 6.0 and synthesized by TSMC .13μm process library.