卡爾門濾波陣列處理器及其容錯設計

Abstract

本論文意圖針對卡爾門濾波器設計一高效率之特殊應用積體電路。由於超 大型積體電路製作技術的快速進步，使得即時應用之卡爾門濾波器的製作 亦變得可能。 首先，我們將提出三個新的矩陣乘法式之心縮式陣列， 並利用數項性能量測以証實本心縮式陣列的確具有較佳的效率及性能。 其次，為提升卡爾門濾波器以心縮式架構實現時的處理速度以及減小其 硬體的複雜度，此三個矩陣乘法式之心縮式陣列將被應用在三個較受歡迎 的卡爾門濾波演算法。此三個卡爾門濾波演算法的數學公式將被重新安排 並針對所應用之心縮式陣列作最佳的分解。因此，將可得到九個新的卡爾 門濾波器之心縮式架構。其中，有兩個架構在速度及硬體複雜度之性能上 均較現有架構中最有效率者為佳。此些優於傳統架構之特性將是卡爾門濾 波器在超大型積體架構以及即時應用上之最佳選擇。 由於現今的 IC 製造技術，使得晶片在生產後仍有許多錯誤及瑕疵發生，所以對大數量 的 VLSI/WSI 的系統上製造存良率太低，而無法接受。另一方面，在運作 時不能保証所有的處理單元不發生錯誤，因此，我們亦將對卡爾門濾波器 的陣列架構導入容錯技術以加強製造存良率和系統的可靠度。 This thesis intends to arrive at an efficient ASIC design for Kalman Filter. First of all, we will propose three new systolic arrays for matrix multiplication. They are shown to be efficient in terms of several performance measures. Next,in order to speed up the systolic implementations of Kalman filters and reduce their hardware complexities, we will apply those three new systolic arrays to three target popular Kalman filtering algorithms. This results in nine new systolic Kalman filters. Among them, two architectures have the best performances in both speed and hardware complexities compared with the existing architectures. However, in fabrication time, manufacturing defects on wafers are inevitable in today's IC technology, so the yield of a WSI system of a large number of PEs is usually unacceptably poor. Therefore, in run time, it is almost impossible to guarantee such an array to have all the PEs running correctly over the time span of a mission. To overcome this problem, we will also incorporate run-time fault- tolerance schemes into Kalman filter system at the array stage to enhance the yield and the reliability.