矽質單晶微波積體電路電晶體之研製

Abstract

為促進單晶微波積體電路的發展,本文提供標準雙極性電晶體與複晶矽射 極雙極性電晶體的製程模組開發,作為將來研製單晶微波積體電路的基本 製程. 獨立元件用完全凹陷場氧化物作隔離,而積體電路則採深溝隔離,再 加上不同離子佈植方式和控制推入的時間及溫度,達到高頻操作元件所需 之雜質分佈. 我們設計多指狀的射極和基極結構及改變射極寬度和長度, 以了解其間各參數的關係. 另外藉由分析測試鍵,得到元件經各製程後之 相關特性,由此調整製程並建立製程模組能力. 結果顯示,鍍完金屬後的元 件,電流增益會變小. 若射極面積愈大,元件的電阻愈小. 而且射極寬度較 大者具有較高的電流增益. For advancing the development of monolithic microwave integr- ated circuit(MMIC), the process modules of standard bipolar jun- ction transistor and poly-emitter bipolar junction transistor are studied in this thesis. These developmental modules will be the basic fabricated processes in the MMIC. The discrete devices are isolated by fully recessed oxidation. The integrated circuit will utilize the trench isolation. By using different implant conditions, drive-in time and temperature, the doping profile will meet the requirement of high frequency operating devices. We design the interdigitated structure for base and emitter reg- ion with various emitter width and length. The information between parameter variations and process conditions can be found via this design. Every process data can be obtained by analyzing the test key. The process modules can be calibrated and set up from the experimental data. The results show that the current gain of the devices are smaller after metallization. The larger emitter area has the lower resistance. Moreover, the current gain is higher if the emitter width is increased.