快閃式電性可抹除式可程式化唯讀記憶體元件穿透介電層的新製程技術

Abstract

本論文提出二種新穎而簡單的製程技術,用以製造出快閃式電性可抹除式 可程式化唯讀記憶體元件所需的穿透介電層.第一種方法是先將一層非常 薄的半球狀複晶矽沉積在矽晶圓上,加以高溫氧化後而形成穿透介電層.經 由此方法,穿透介電層會形成不同粗糙程度的界面,尤其是在介電層與矽基 板交界面上所形成的微尖端.由於這些微尖端會增強局部的電場強度,使得 這新式穿透介電層具有相當高的電子穿透效率.因此,傳導電流大幅提升. 這將使得非揮發性記憶體元件的操作電壓大幅降低,以符合極大型積體電 路的要求.同時,此新式介電層更擁有高的可靠度,低的電荷捕獲率,穩定的 界面狀態以及大的電流不對稱性等優點.第二種方法同樣地先將一層非常 薄的氮化矽沉積在矽晶圓上,加以高溫氧化後而形成穿透介電層.藉由材料 分析,發現氮不對稱地堆積在介電層之兩側界面.由於氮的位置及濃度對電 性會有不同的影響,因而導致大的電流不對稱性.其應用於非揮發性記憶體 元件,可以得到記憶速度加快以及在高電場下電荷保存時間增長的優點.同 時,由於氮會增強介電層的界面強度,使得界面狀態產生及可靠度這兩項電 性也獲得改善. In this thesis,two novel and simple technologies are proposed to fabricate the tunneling oxides for the flash EEPROM devices. For the first method,the novel oxide was fabricated by thermal oxidation of a ultrathin hemi-spherical-grain polysilicon film. The rough interface of the oxide,especially microtips on the bottom interface,results in the enhanced injection efficiency due to the field enhancement.Hence the operation voltage of EEPROMs is reduced to satisfy the requirements of the ULSI scale- down.The novel tunneling oxide exhibits a higher reliability,a lower electron trapping rate,a stable interface state and higher asymmetric current in comparison with a control oxide. For the second method,the oxide was fabricated by thermal oxidation of a superthin silicon nitride film.From AES analysis, nitrogen asymmetrically piles up at top and bottom interface of the oxide.Due to the various effects of nitrogen distribution and concentration on the electrical performance,the asymmetric injection polarties are obtained. Meanwhile,the reliability and interface state generation are also improved because the strong Si-N bonds strengthen the interface hardness of the oxide.