以有紋路之矽表面成長穿隧氧化層於電子可擦拭儲存可程式化唯讀記憶體之研究

Abstract

本論文提出新穎製程技術,以製造出快閃式電性可抹除式可程 式化唯讀記憶體元件所需的穿隧介電層. 首先,以低壓化學氣相沈積( LPCVD)方式,在矽晶圓上沈積一層約10nm的複晶矽,再以900℃ 高溫將此複 晶矽完全氧化而形成氧化層 ,此氧化層將視為犧牲氧化層,然後將此氧化 層去除,此時矽晶圓表面將變成有紋路表面,在氧化後形成穿隧介電層,經 由此方法穿隧氧化層會形成不同粗糙程度的界面,尤其是在介電層與矽基 板交界上會形成微尖端.由於這些微尖端有增強局部電場強度,使得這新式 穿隧介電層具有相當高的穿透能力,因此傳導電流將可大幅提升.這將使得 非揮發性記憶體元件操作電壓大幅降低, 以符合超大型積體電路要求,同 時新式穿隧氧化層具有較高的可靠度,低的電荷捕捉率,穩定的界面狀態, 及電流不對稱性等優點. In this thesis, novel and simple technologies are proposed to fabricate the tunneling dielectric for the flash EEPROM devices. Firstly, a thin polysilicon (about 10nm) layer was deposited on Si substrate by low-pressure chemical vapor deposition (LPCVD) and dry oxide film was grown at 900℃ in O2 ambient. The polysilicon film and Si substrate were both oxidized during thermal oxidation. This oxide film was served as a sacrificial oxide. After stripping this sacrificial oxide, a textured Si surface was obtained. Tunneling oxide grown on this textured Si surface has different roughness degree. The microtips have been found to be at the bottomand top interface of the oxide. These microtips result in the localized fieldenhancement and enhance electron injection into the oxide. Therefore, the operation voltage of EEPROM devices is reduced to satisfy the requirements ofULSI scale-down. Also, the novel tunnel oxide exhibits higher reliability,lower electron trapping rate, stable interface state and higher asymmetric current in comparison with control oxide.