以溶膠-凝膠法製備PLT鐵電薄膜及其電性之研究

Abstract

本論文以溶膠-凝膠法成功地製備出不同鑭濃度(0~28 mol%)結果的PLT 鐵 電薄膜,以Pt/Ti/Si為基板,經600?C燒結30分鐘,結果可得到無龜裂 且晶 粒大小均勻(約100nm)且表面平坦的PLT薄膜.本實驗所製備的PLT0, PLT10,PLT28和PLT28薄膜,其介電係數分別為 198,256,370,和588,關於 PLT鐵電薄膜的主要傳導機構,本文亦加以探討.利用傳統積體電路製程,以 PLT0,PLT10,PLT20和PLT28為材料所製備 出的PLT薄膜電容,其電荷儲存密 度分別為0.35,0.46, 0.66和1.03uC/cm2 -V. The La-modified lead titanate(PLT) with various lanthanum contents(0~28mol%)has been prepared by sol-gel processing. The PLT thin films deposited on Pt/Ti/Si substrate at 600?C for 30 min. possess crackinng-free, uniform grain size(about 100nm), and flat surface properties. The dielectric constants of the PLT thin films are 198, 256, 370, and 588 for PLT0, PLT10, PLT20, and PLT28, respectively. The dominant conductance mechanism of the PLT thin film has also been discussed. The conventional integrated-circuit processing has been applied to fabricated the PLT thin film capacitors. The charge storage densities of PLT thin film capacitors are 0.35, 0.46, 0.66, and 1.03uC/cm2-V for PLT0, PLT10, PLT20, and PLT28, respectively.