應用於MPEG-2解碼器之反向離散餘弦轉換的設計與實現

Abstract

視訊通訊在今天被廣泛應用於許多領域。為了達到更佳的傳輸效率，影像 壓縮已經變成視訊產品中的一項重要技巧。而影像壓縮的標準化為視訊產 品的設計者和生產者提供了一個依循的標準。MPEG-2便是一個運用於高畫 質影像應用的壓縮標準。在本篇論文中，我們提出一個運用於MPEG-2解碼 器的反向離散餘弦轉換模組。我們使用分散式運算的觀念和唯讀記憶體– 累加器的架構來實現八乘八的反向離散餘弦轉換。為了減少使用的硬體， 我們只使用了一個一維反向離散餘弦轉換模組來計算兩維的反向離散餘弦 轉換。同時，運算的精確度遵循MPEG-2標準的規定。我們的架構的主要好 處在於面積的節省，而運算速度符合我們的要求。除此之外，我們還實現 了反向掃描模組和反向量化模組。我們使用 Verilog模擬器來進行設計， 並將其對映至聯華電子公司的0.8微米標準元件庫。 Video communication is widely used in many areas today. To achieve higher transmission efficiency, image compression becomes an important technique in video applications. The standardization of image compression will give a criterion to the designers and manufacturers of video products. MPEG-2 is such a compression standard for high quality image applications. In this thesis, we propose an inverse discrete cosine transform module for MPEG-2 decoder. Using distributed arithmetic concept and ROM-accumulator architecture, we implement a 8x8 IDCT. To reduce the hardware cost, only one 1-D IDCT module is used to compute 2-D IDCT in our architecture. Meanwhile, the accuracy of computation results follows the MPEG-2 standard specification. The main merit of our architecture is in area saving, and the operation speed can satisfy our requirement. In addition, the inverse scan module and inverse quantization module are also developed. We have designed these modules using Verilog simulator and mapping the circuits to UMC 0.8um Standard Cell Library.