一個經濟 可程式化的腓特比解碼器

Abstract

本篇論文敘述一個可程式化的腓特比解碼器(Viterbi decoder)及其理論 架構。此系統可應用在 2 ≦ m ≦ 4 之迴旋碼(Convolutional Code)， 並且可用 100 MHz 之時序波(clock)驅動。此經濟之設計乃在於精簡記憶 體、繞線面積和Add-Compare-Select (ACS)此單元之速度加快。在安排餘 存記憶體(Survivor Memory Management)的方法上，我們採用回頭找( Trace-back)的方法，如此便可節省繞線面積。在餘存記憶體的設計上， 我們用一個暫存器(register)去儲存節點值(node content)，並且用的 SRAM，是單埠輸入、單埠輸出，如此，便大大節省記憶體面積。在ACS速 度的改善上可分兩個方面，一是用兩個ACS做平行處理(parallel processing)，另一是在ACS內部處理上運用管線(pipeline)來增加產出 率(throughput)。此架構隨即轉換成電路設計，並且Layout成Chip。此 Chip之面積為0.4cm*0.3cm最快的時序速度為100MHz。在論文最後，我們 討論如何設計能符合一般應用之可程式腓特比解碼器。 In this thesis, an algorithm and an ASIC architecture for programmable Viterbi decoder are presented. This system theoretically could be driven by 100MHz singal phase clock, and has the programmable ability to decode 2 ≦ m ≦ 4 convolutional code. The efficient design comes from the reduction of memory area, wiring area, and the speed up of add- compare-select(ACS) operation. The trace-back method is applied to reduce the wiring area. The path memory which stores the surving paths is reduced as the node register cell is one bit cell. And the SRAM cell is designed in an asymmetric way to apply the one port in, one port out operation. This will also reduce the memory size. And the 2-ACS's parallel processing, together with the internal pipeline schedule of ACS unit enchances the ACS operation speed. The architecture is then mapped on circuit design, and layout implementation is made by using TSMC 0.8mm CMOS SPDM technology. The chip area is 0.4cm*0.3cm and the maximum clock rate is 100MHz. In the end of the thesis, we will discuss the ways to design the programmable Viterbi decoder for versatile use.