完整後設資料紀錄
DC 欄位語言
dc.contributor.author吳建德en_US
dc.contributor.authorChien-Te Wuen_US
dc.contributor.author李鎮宜en_US
dc.contributor.authorChen-Yi Leeen_US
dc.date.accessioned2014-12-12T02:12:12Z-
dc.date.available2014-12-12T02:12:12Z-
dc.date.issued1993en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT820430074en_US
dc.identifier.urihttp://hdl.handle.net/11536/58076-
dc.description.abstract本篇論文主要是提出一個能夠執行各種不同視訊處理演算法的可程式視訊 處理器。在這視訊處理器,我們針對各種不同視訊處理演算法的複雜度加 以分析,以設計出一個能夠供應大量計算效能的視訊處理器。另外記憶體 頻寬的問題一直是處理大量視訊資料的主要頻頸。在我們的設計裡也針對 這問題給予詳細的分析與設計,並據此解決I/O的頻寬問題。同時我們也 深入探討此視訊處理器各個方塊(例如加法器、乘法器和內建記憶體 )的 電路設計技術,以便使這視訊處理器能夠運作在100MHz的時脈速度。以此 時脈速度,一些標準的視訊處理演算法(如 H.261、JPEG....等)能夠在單 一顆視訊處理器執行完畢。最後,我們也提出一個有效的設計方法 (Design Methodology),根據這方法我們小心的規劃有關之時脈訊號分 佈 (Clock Distribution) 和電源供應訊號分佈 (Power Distribution) ,並且利用 TSMC 0.8um CMOS SPDM 的製程技術去製作此一符合面積效能 的視訊處理器。 In this thesis, we present a programmable VSP (video signal processor) design targeted to any video algorithm applications. In this design,offering sufficient computational power to cope with algorithm complexity and reducing memory bandwidth to solve I/O bottleneck remain the two key issues to be handled carefully as VLSI technology improves. We also present the circuit techniques and design flow under development in our research Lab. In the design flow, we briefly discuss the design methodology and verification approch under our CAD environment. We then give an in-depth discussion of the circuit design techniques to highlight how a 100MHz clock speed can be encountered. Much effort is focused on both datapath unit and high speed on-chip SRAM which are the key modules of the VSP. In the end, layout strategy, clock distribution and power distribution is given to achieve an area-efficient solution based on TSMC 0.8um CMOS SPDM technology.zh_TW
dc.language.isoen_USen_US
dc.subject視訊處理器;記憶體產生器;乘法模組產生器;加法模組產生器;鎖相迴路zh_TW
dc.subjectVideo Signal Processor; Memory Generator; Multiplier Generator; Adder Generator; Phase-Lock Loopen_US
dc.title可程式視訊處理之設計與製作zh_TW
dc.titleDesign and Implementation of a High Performance Programmable Video Signal Processoren_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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