應用於液晶監視器訊號擷取電路之鎖相迴路式頻率合成器之設計

Abstract

本論文描述一個應用於液晶監視器訊號擷取電路之鎖相迴路式頻率合成器之設計，其為一內外時脈之介面，具有將晶片內外的時脈之相位鎖定而以消除內外脈波的時間延遲，並具有將內部之時脈倍頻之功能。 這個晶片採用 0.35μm 1P4M CMOS製程技術，且已經由國科會晶片製作中心下線製作實現。晶片內部包含一個鎖相環和一個低功率(功率/頻率)的可程式除頻器，做為頻率合成用。其工作電壓為3伏特，輸入時脈頻率從15.75至66.67KHz，來合成出符合在CGA、VGA、VESA(800*600)、VESA(1024*764)與SUN的應用，其合成之頻率範圍為12MHz至100MHz，其並需要輸出32個相位提供系統做微調，因此使用16級的壓控振盪器。且為能在不同之顯示模式能得到較好的效能，因此內部有某些參數可以被選擇，如內部壓控振盪器被設計成四個不同增益頻段(頻率/電壓)，電荷充放電路之電流大小從6.25μA到700μA被分為8段，而可程式除頻器的範圍是在100至4095(共12級)。 此晶片經量測後顯示其鎖相迴路能正常鎖住相位，但因壓控振盪器輸出訊號之歪斜(skew)影響，使可程式除頻器第一級計數器工作不正常，因而使輸出訊號頻率約為所想要之頻率之一半。而量測輸出訊號為50MHz時之時脈抖動為18.67 ps (rms)，而消耗功率為30mW。

This thesis describes the design of a PLL-based frequency synthesizer for ADC in LCD Monitor. It is the interface between internal clock and external clock. It serves to lock the external and internal clock phases to achieve synchronization. It also generates an internal clock which is multiple times of external clock. This is called pixel clock because the analog video signal is digitized by ADC at this frequency. This chip was implemented using a 0.35μm 1P4M CMOS process. This chip includes a PLL and a low power (power/frequency) programmable frequency divider for frequency synthesizer. The supply voltage is 3 V and input frequency is chosen from 15.75, 31.5, 48.08, 60.02, and 66.67 KHz, which is used to synthesize the internal clock for CGA, VGA, VESA (800*600), VESA (1024*764) and SUN application respectively. The frequency synthesizer is designed to synthesize the internal clock from 12 MHz to 100 MHz. The frequency synthesizer needs to generate 32 phases to fine tune the system clock, so it utilizes a 16-stages voltage controlled oscillator. To get better performance in different display modes, some parameters are programmable. For example, the voltage controlled oscillator has four different gains (frequency/voltage), the charge pump current has 8 choices from 6.25 μA to 700 μA, and the range of the programmable counter is 100~4095 (12 stages). This chip had been tested and the PLL can lock to the input frequency. But due to the skew of the VCO’s outputs, the first stage counter in programmable counter does not perform counting. As a result, the synthesized frequency is approximately one half of the desired frequency. The measured jitter is 18.67 ps (rms) at 50 MHz and power consumption is 30 mW.