一種新型數位鎖相迴路DSL之超大型積體電路設計

Abstract

在本論文中，我們提出一種新型的數位鎖相迴路，稱之為Digital Sinlock Loop(DSL)。它主要是由Digital TanLock Loop(DTL)改進而來。 除了保留原先DTL的優點，例如鎖碼範圍、線性的相位差特徵曲線以及易 於分析的特性外，它的應硬體遠比DTL為小，若就積體電路佈局而言，其 面積可減為原先的三分之二。此乃由於它只須用一個類比至數位轉換器即 可正常運作，是為其最大特點。 我們將此鎖相迴路應用在以π/4-DQPSK 調變之數位蜂巢式汽車電話系統上。此系統中，信號傳輸不僅會受到雜 訊(AWGN)的干擾，也會受到衰減效應(fading effect)的影響。根據電腦 模擬的結果顯示，在數位蜂巢式汽車電話系統中，N-phase DSL的表現與 N-phase 外，根據模擬的結果，我們完成了此一新型鎖相迴路硬體設計與 積體電路佈局，並以電路模擬程式HSPICE及IRSIM驗證其功能正確無誤。 In this thesis,a new digital phase-lock loop(DPLL),denoted as Digital SinLock Loop(DSL) is proposed.The DSL is a non- uniform-sampling DPLL whose phase error detector,using the arcsine function with the quadrature samples of incoming has a liner characteistics with a period of 2π.The N-phase for tracking suppressed-carrier N-ary phase-shift Keying(PSK) singals. In this thesis,the application of the N-phase DSL to the digital cellular radio with π/4-DQPSK modulation is Since the N-phase DSL is mainly evolved from the N-phase can be shown that both have the same characterics, the similar structure and performances.However,both the complexity and size of the N-phase DSL are much less than those of the N-phase in addition to the software simulations, aVLSI hardware implementation of the N-phase DSL is DSL is completed and been investigated successfully.