視訊處理器之設計

Abstract

本論文完成一名為4P-VSP的視訊處理器的設計，它最大的執行能力為400 MOPS。使用高度平行架構將四個處理單元置於一顆晶片中，比傳統的視訊 處理器約快十倍。此顆4P-VSP有下列之特徵：使用非一致性的處理單元， 可省下面積卻依然可以達到平行處理的目的；富有彈性變化的定址模式， 可以增加資料傳輸率，採用雙平面瓦勒思樹狀結構的乘法器及混合式基數 二的加法器，以配合高速的需求，簡易性的邏輯運算單元易解碼......等 等。 4P-VSP是為了各種影像處理而設計；採用多個4P-VSP處理器完成的 架構，亦可適於高傳輸率的影像處理例如MPEG。此晶片是用台灣積體電路 公司的0.8um製程，晶片大小約1.42cm*1.28cm，電晶體數目約為六十萬個 。 A single-chip video signal processor named 4P-VSP capable of attaining a maximum performance of 400-MOPS (mega operations per second) is proposed. Highly parallel architecture which allows four processing units to be integrated into one chip are implemented and that have roughly 10 times the performance of conventional VSP's. The key features of 4P-VSP are: non- uniform structured PEs with more area efficiency was used under parallel processing, flexible addressing mode was designed for high throughput data flow, dual array Wallace tree structure for multiply and hybrid radix2 adder for high speed requirement was adopted, simplified ALU structure was proposed for easy decoding, ...etc. The 4P-VSP is designed for a maximal set of applications in image processing. Some useful multi-VSP architectures were also proposed for high throughput image data, such as MPEG. The chip layout is designed with 0.8 CMOS TSMC's technology, having a 1.42cm*1.28cm diesize contains about 600k transistors.