運用信號轉換機率之金氧半電路的功率估計

Abstract

功率的消耗在超大型積體電路上日趨重要。近年來有許多的學術研究投入 在功率估計和低功率設計上。而信號線的兩大統計特性：高態機率和轉換 機率，在大部份的功率估計和功率降低技術上扮演著舉足輕重的角色。首 先，在這論文裡提出一個新的方法來計算信號的高態機率和轉換機率。一 般線路在運作時，常會因不同的邏輯閘延遲，而在各信號線上有不當的邏 輯準位跳動產生。這新方法會準確地將這些跳動計算進去。而且，附帶地 ，無效路徑問題和最長路徑的搜尋也被解決。另外我們提出一個新的根據 電路中各信號線的高態機率和轉換機率來估算電路功率的方法。這方法會 對電路中各邏輯閘建立一個相對應的模型。它不只考慮邏輯閘內部寄生電 容的充放電，還兼顧電容耦和效應所造成的複雜功率變化。頗令人滿意的 是，我們試了許多電路並與精確的 SPICE模擬比較，平均只有百分之十以 內的誤差。 Recently, power consumption becomes an important issue in VLSI circuit designs. Many proposed researches devote to the topics of power estimation and low power design. In these researches, signal probability and transition density of the signal in circuit play important roles in most estimating methods and power reducing technique. In this thesis, a new method for calculating the signal probability and transition density is proposed firstly. The glitches due to general gate delays are precisely calculated. Another advantage of this method is that the false path problem and critical path searching are solved as by-products. Based on the data of all signal probabilities and transition densities of a circuit, a cell-based power estimation (CBPE) method is proposed in this thesis. In this method, a power dissipation model considering the charging and discharging of gate internal nodes and capacitance feedthrough effect is built. For a set of benchmark circuits, experimental results show that the power dissipation estimated by CBPE has on average 10-percent larger than the exact SPICE simulation while the CPU time is more than two order-of-magnitudes faster.