組合邏輯電路之訊號轉換機率分析

Abstract

近年來, 功率消耗在超大型積體電路上日趨重要, 許多的學術研究紛 紛投注在功率估計和低功率電路設計的研究課題, 其中, 尤以功率估計更 受注意, 因為一個良好的低功率設計環境, 需要一個準確而有效率的功率 評估工具來協助評估那一種電路較省功率. 本論文將分別針對在零延 遲模型及一般延遲模型, 提出改進的新演算法來估算組合邏輯電路中各結 點的高態機率和轉換機率, 其特點是不構建廣域的二元決定圖( globalBDD ) . 在零延遲模型中, 利用馬可夫鍊( Markov Chain )模型來 考慮電路中內部結點之空間上及時間上訊號轉換的關聯性; 而在一般延遲 模型中, 提出一個公式來估算因多餘訊號轉換對訊號轉換機率的影響. 我們的功率估計方法可以提供高準確度的結果和低運算時間, 較高的準確 度是因為考慮了每個輸入訊號之間空間及時間的相關性. 此外, 在計算機 率上使用遞增近似法也降低了運算時間, 因為我們所提出的方法不需要構 建廣域的二元決定狀態圖, 所以能夠處理較大型的積體電路. 令人滿意的 是, 我們試了許多電路並與精確的VERILOG 模型比較, 在零延遲模型及一 般延遲模型中平均只有百分之十以內的誤差. Recently, power consumption becomes an important issue in VLSI circuitdesigns. Many researches are devoted to the studies of estimation and low power circuit design. Among these topics, power estimation is paid much more attention, because a low power design environment needs an accurate and efficient power estimation tool to evaluate the effectiveness of low power circuit design. In this thesis, we have presented an improved algorithm to estimate the signal probability and switching activity at all nodes in a combinational logic circuit under zero_delay and general_delay models. Under zero_delay model, complex spatiotemporal correlations among the circuit inputs and internal nodes are considered by using a Markov Chain model. Under real_delaymodel, a formulation is presented to estimate the transition densities by considering the contribution of glitches. Our approach could provide more accurate results with lower CPU time. Thehigher accuracy is achieved by considering the spatiotemporal correlation of the signal on each primary input. The lower CPU time is also achieved by usingthe incremental approach for probability calculation. Our approach is able tohandle large circuits, since it does not need to construct global BDDs for theprobability calculation. For a set of benchmark circuits, experimental resultsshow that the signal probabilities and transition densities estimated by our methods have on average 10 percent less than the exact VERILOG simulation under zero_delay model and unit_delay model.