標題: | 利用克霍諾神經網路的動態影像辨認系統之晶片設計 The Chip Design of Moving Object Recognition System with Kohonen Neural Network |
作者: | 徐永傳 Yon-Chun Shie 吳重雨 Dr. Chung-Yu Wu 電子研究所 |
關鍵字: | 動態影像辨認; 克霍諾神經網路;Moving Object Recognition; Kohonen Neural Network (KNN) |
公開日期: | 1993 |
摘要: | 本論文提出了一個晶片組設計的動態影像辨認系統,我們可從一系列隨時 間變動的影像資料中萃取出其中的運動物體,並加以分類辨認。由於二維 影像的資料量很大,若要對其做快速的運算,則平行處理的方式是最佳的 途徑。本論文研製了二個具有平行處理能力的晶片,其中一個晶片適合萃 取動態影像,它是以1.0um BiCMOS 製程製造的。另一個晶片是以0.8um CMOS 製程製作的克霍諾神經網路,利用這個晶片我們可以組成一個具有 分類及辨認功能的階層式克霍諾神經網路。同時, 為了因應更大的影像 資料, 這兩個晶片可予以擴充連接成更大的網路。最後, HSPICE 的模 擬結果顯示出我們的設計是正確的。 The chip design of a moving object recognition system is proposed. In this design, the moving object from a sequence of time-varying image data can be extracted and recognized as a membership grade of some class. Because of the large amount of data in the two-dimensional image, parallel processing is supposed to be the best candidate in solving this kind of problem. Two chips are designed in this thesis to realize parallel processing of image data. One is the prototype chip for moving object extraction and is fabricated by the BiCMOS 1.0um double poly double metal process technology. The other is the Kohonen neural network and is fabricated by the CMOS 0.8 um double poly double metal n-well process technology, which can be used to build a hierarchical Kohonen neural network for classification. Both of these two chips can be expanded to increase the size of image that can be processed. The HSPICE simulation results from these prototype chips have demonstrated the correctness in the design work and suc- cessfully verified the chip functions. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT820430101 http://hdl.handle.net/11536/58106 |
顯示於類別: | 畢業論文 |