無線電之中頻解調器的類比 CMOS 電路技術

Abstract

本論文提出一個可以工作在 10 到 70 MHz 的 CMOS 單晶中頻解調器的電 路技術. 此解調器乃是用一個單端輸入級去產生一個低雜訊放大器, 以達 到最好的免疫程度. 而此低雜訊放大器的等效雜訊源為 10 nV , 亦即在 1 MHz的頻寬內此雜訊的大小為 10 uV. 可變增益放大器對此解調器約產 生 40 dB的動態範圍. 其次, 在一個 5伏特的單電源供應器中, 一個對稱 的 A類輸出驅動器已被最佳化到能符合大信號失真的範圍 , 並做為此解 調器的緩衝級. 此緩衝級能夠驅動一個峰值至峰值為 3伏的信號到一個 100 pF 的負載上, 並使失真在 1% 之內. 此中頻解調器已經做在一個標 準 0.8u n 型井的 CMOS 製程中. 此 CMOS 製程的技術所完成的解調器和 類似 BJT的製品比較起來會產生更高準位的整合效果 . 最後, 此解調器 中關於低雜訊放大器, 類比乘法器, 和可變增益放大器的電路技術都會被 詳細的分析和討論. This thesis presents a monolithically integrated CMOS IF demodulator that operates at 10-70 MHz. The demodulator uses a single-ended input stage to realize optimal noise performance. The measured equivalent input noise of the low noise amplifier (LNA) is as low as 10 nV per squart hertz (i.e., 10 uV with 1 MHz bandwidth ). Variable gain amplifier (VGA) gives the de- modulator an electrical input dynamice range of about 40 dB. A differential symmetrical class-A output buffer is optimized to large signal distortion performance with 5-V single power su- pply. The buffer is capable of driving a 3-V (peak-to-peak) signal to a 50 omega load with a total harmonic distortion less than 1%. The demodulator is fabricated in a standard 0.8 u n- well CMOS process. The technology choice results in a high level of integration compared with similar bipolar technology demodulator. The die area is 3.1mm * 3.1mm. Finaly, design detail and per- formance concerning the preamplifier(LNA), mixer(analog multi- plier), and variable gain amplifier (VGA) are analytically de- scribed.