積體電路生產線上考慮缺陷群聚現象的製程管制圖

Abstract

積體電路 (integrated circuit，IC) 的晶圓表面在繁複的製程中，難免都會形成各種的缺陷。其中有些會直接影響晶片的功能表現，降低晶片的良率 (yield)；至於其他的缺陷雖不至於降低良率，卻也極可能對晶片的可靠度 (reliability) 產生不良影響。為了提升IC產品的良率與可靠度，必須在IC生產線上實行統計製程管制 (statistical process control, SPC) 監測製程缺陷的分布行為，以掌握製程狀況，針對製程異常採取因應措施，並提供線索以協助分析製程缺陷的形成原因。 晶圓上的缺陷點數太多和缺陷群聚 (cluster) 程度過於嚴重，都會影響IC產品的良率與可靠度。因為傳統的缺陷點數管制圖已不適用於超大型積體電路下的製程，而新進論文所提議之缺陷點數管制圖並不能偵測出缺陷群聚的現象。所以本研究的主旨乃在引用一些分析空間分布型態的方法，分別設計管制圖 (control chart) 以偵測這兩種製程異常狀況。論文的最後並以目前半導體業界的實例，驗証本文所倡導之方法的可行性。

During the complicated production process in integrated circuit fabrication, surfaces of wafers are vulnerable to various types of defects. Some of them having impacts on the function of IC chips affect the yield of chips; and yet many defects other than Idler defects affect the reliability and performance of IC products. In order to promote the yield and reliability efficiently, therefore, on the production lines we must conduct statistical process control (SPC) which serves to display the process status, detect significant process variations, and give clues to help find the defect-causing fabrication processes. The number of defect counts and the extent of defect-clustering both influence the yield and the reliability of IC products. While conventional control charts for defects are no longer valid under VLSI technology and new methods proposed by papers are unable to detect defect-clustering situations, in this research various methods of spatial pattern analysis are adopted to construct new control charts to detect the situations of too many defects and too much defect-clustering. Further, at the end of the study, an empirical example from IC manufacturing industry is given to examine the performance of the proposed procedures.