應用粗糙表面之複晶矽形成新奇電容器之研究

Abstract

在動態隨機存取記憶體元件縮小化的過程中，積體電路元件愈來愈小。因 為隨著記憶體密度增大，內部元件的縮小，但電容量不能隨之成比例減少 ，必須在有限的面積下提供足夠大的電容值。因此先進的儲存式電容結構 是必需的，許多方法被發展出來以滿足這個需求：(1)降低介電層厚度 ；(2)改變介電層材料；(3)增大電極表面積。其中降低介電層厚度和改變 介電層材料方面，已經有許多文獻探討並且被廣泛地應用，因此增大電極 表面積似乎是另一種具有潛力的改善方法。有一種增大電極表面積的技術 則是將磷摻雜過的多晶矽以磷酸浸煮處理而成多孔矽，利用此一方法可以 在堆疊電極表面佈滿孔洞，達到有效增大電極表面積的目的。本論文將針 對不同的磷摻雜濃度及不同的磷酸浸煮時間和溫度作探討，我們發現經過 磷摻雜的多晶矽在晶界區域有良好的蝕刻效果，並在表面形成島嶼狀的凹 凸結構，我們利用掃描式電子顯微鏡觀察其表面的形態。另一發現是磷酸 對晶界的區域作選擇性的蝕刻，因晶界區域有較多的晶體缺陷及低能量晶 格，使得摻雜的磷原子容易積聚在晶界區域，而造成較明顯的蝕刻效果， 藉以上的結果推導出磷酸浸蝕多晶矽表面的機構。利用以上方法所準備的 多晶矽當作電極，再成長介電層製作成電容，並觀察其面積效應對電容值 的影響。此粗糙表面的多晶矽電極能有效的增加電容值，並具有應用於高 密度動態隨機存取記憶體之潛力。 For the down-scaling of DRAM cells, an advanced storage capacitor structure is required to provide sufficiently large capacitance in a limited area.Many researches have been reported to meet the requirements. By immersing into the H3PO4 solution, the phosphorous-doped poly-Si films can achieve the rough surface.To explore the etching mechanism,the polySi films with different doses annealed various temperatures were utilized Furthermore, the etching time and the temperature of the H3PO4 solution were also investigated to optimize the etching process. From the SEM photographs,micro- cavities and cracks are observed,leading to the rough morphology of the poly- Si films after the treatments. According to the TEM photographs, high etching rate at the grain boundaries in the H3PO4 solution can be concluded to be the main reason of the rugged polysilicon. The rugged polysilicon can be used as the bottom electrode of the novel capacitor. 1.4 ~ 1.7 times storage capacitance can be obtained with the novel capacitor.This capacitor is easier to be fabricated and fewer process step are needed as compared with other proposed techniques. This novel capacitor is thus a promi- sing candidate for the high-density DRAM's.