高品質動態隨機存取記憶體記憶胞之電容量及記憶時間研究

Abstract

摘要 本論文研究方向，主要是以增進動態隨機存取記憶體記憶胞復新時間(refresh time)為研究方向及目標。可藉由兩種方式達成，一是增加動態隨機存取記憶體記憶胞電容量，一是減少動態隨機存取記憶體記憶胞漏電流量。因此本論文第一階段是研究以皺褶表面電極板增加電容量。在我們的研究中，成功使用快速升降溫化學氣相沉積系統(RTCVD)來製造皺褶表面電極板(rugged poly-Si)，它不只可適用於12吋晶片使用，同時更具有較寬的生成條件，且它的效率面積是投影面積之2.9倍。本論文第二階段是以研究五氧化二鉭(Ta2O5)當電容之絕緣層，其介電常數約為二氧化矽的四倍。我們使用快速升降溫氮化預處理電極板表面及快速升降溫氧化後處理五氧化二鉭薄膜去降低電容之漏電使漏電小於10-8 A/cm2，這兩階段都達成我們增加電容量之要求。 在減少動態隨機存取記憶體記憶胞漏電流量方面，本論文第三階段是研究如何增進動態隨機存取記憶體記憶胞記憶時間(retention time)，簡單的說是使電荷留在電容時間久一些。基本上動態隨機存取記憶體記憶胞記憶時間可分為二大分佈，一為主分佈區(main distribution)二為次分佈區(tail distribution)，有不同的機制分別影響這二區。增加動態隨機存取記憶體記憶胞電容量是影響主分佈區，但是動態隨機存取記憶體記憶胞復新時間(refresh time)卻是由次分佈區所限制。在論文中主分佈區是由二氧化矽與矽晶介面之陷阱中心(trap center)及矽氫陷阱中心(Si-H trap center)所產生之生成-覆合電流(G-R current)所影響，次分佈區是由高密度電漿化學氣相沉積(HDP)之應力造成差排(stress induced dislocation)及爐管氧化造成差排(oxidation induced dislocation)及溝槽蝕刻輪廓(trench etching profile)產生的熱游子場射出電流(TFE)所影響。本論文最後是對降低動態隨機存取記憶體記憶胞之接觸電阻研究，因為動態隨機存取記憶體記憶胞之接觸電阻變高會使有效之復新電壓變低，且使動態隨機存取記憶體記憶胞復新時間低於容許下限，所以降低動態隨機存取記憶體記憶胞之接觸電阻是必要的工作。

Abstract The main goal of this thesis is to improve the refresh time of DRAM cell. It can be accomplished by two approaches. The first approach is to increase the storage capacitance of the cell, while the other approach is to reduce the junction leakage current of DRAM cell. For increased storage capacitance, polycrystalline silicon film with a rugged surface (i.e., rugged poly-Si) was applied. The rugged-poly was deposited by a single-wafer rapid thermal chemical vapor deposition (RTCVD) system, suitable for 12-inch wafer fabrication. In this thesis, the rugged poly-Si films have been successfully fabricated to serve as the bottom storage electrode for the stacked capacitor in dynamic random access memory cells. Our study suggests that the rugged poly-Si is actually formed by the nucleation generation on the amorphous silicon surface and subsequent crystalline growth during the annealing step following deposition. An effective surface area of approximately 2.9 times that of a conventional poly-Si film electrode is obtained. In addition, we have fabricated and studied the electrical and physical characteristics of Ta2O5 films on rapid thermal nitrided (RTN) rugged polycrystalline silicon electrodes for 256M dynamic random access memory (DRAM) application. To overcome the higher leakage current on Ta2O5 films with rugged poly-Si bottom electrodes, we have successfully employed a light oxidation on rugged poly-Si grains for improving the acute angle of surface morphology, and a post-treatment with rapid thermal nitridation of N2O on Ta2O5 films to reduce the leakage current. The successful integration of Ta2O5 film with rugged poly-Si makes it very promising for future 256M dynamic random access memory (DRAM) application. Since the retention time distribution of DRAM consists of a ‘tail distribution’ and a ‘main distribution’. Increasing the storage capacitance only improves the ‘main distribution’ of the DRAM array, but it does not change the tail distribution. Since the refresh characteristics of a DRAM array are determined by the worst-case bits represented by the ‘tail distribution’, so increasing the storage capacitance does not improve the overall refresh characteristics of the DRAM array. The ‘tail distribution’ is found to be affected by thermionic field emission (TFE) current of dislocation and stacking faults, while the ‘main distribution’ is affected by generation-recombination (G-R) current of SiO2/Si interface trapped center and H-atom trapped center. We have performed a detailed study, and found that the ‘tail distribution’ is affected by HDP, furnace oxidation, and etching profile processes. In contrast, we found that the ‘main distribution’ is strongly affected by H2 plasma treatment, and HDP trench filling processes. In this thesis, we have also performed a detailed study on how to optimize shallow trench isolation for DRAM application. The retention time distribution is improved in new DRAM generation by the new STI isolation process. However, the degree of improvement is retarded if furnace linear oxide linear is used. The control of defect generation is therefore very important to improve the retention time distribution. Finally, the effects of contact resistance of the refresh characteristics of DRAM cell were studied. Silicidation process is optimized in order to obtain low contact resistance. We found that the contact resistance of the sample with TiN capping layer is lowered by 10-15% and the nature good yield (minimum refresh time of DRAM up to 80 ms) is higher by 19.7% than those of the sample without TiN capping layer,. Abstract (in Chinese) Abstract (in English) Acknowledgment (in Chinese) Contents Table Captions Figure Captions Chapter 1 Introduction 1-1 Overview of challenges for stacked DRAM cell 1-2 Motivation 1-3 The Outline of this thesis Chapter 2 Rugged polycrystalline Silicon Film Formed by Rapid Thermal Chemical Vapor Deposition for Dynamic Random Access Memory Stacked Capacitor Application 2-1. Introduction 2-2. Experimental Procedure 2-3. Results 2-3.1. Capacitance dependence on growth and annealing conditions 2-3.2. Effects of sublayer conditions on the crystallization process of rugged poly-Si 2-3.3. Electrical characteristics of a stacked capacitor with rugged poly-Si as the storage electrode 2-4. Discussion 2-4.1 Formation of rugged poly-Si electrodes using a RTP system 2-4.2 Monitoring the crystallization process of rugged poly-Si 2-4.3 Electrical characteristics of a stacked capacitor with a rugged poly-Si electrode 2-5.Conclusion Chapter 3 Leakage Current Reduction of Chemical-Vapor-Deposited Ta2O5 Films on Rugged Polycrystalline Silicon Electrode For DRAM Application 3-1. Introduction 3-2. Experimental Procedure 3-3. Results and Discussion 3-4. Conclusion Chapter 4 Shallow Trench Isolation for Advanced DRAM Process Partial A: Improved STI-CMP Technology for micro-scratch issue 4-1. Introduction 4-2. Experimental 4-3. Results and Discussion: 4-4 Conclusion: Partial B: Advanced STI process 4-5. Trench Definition and measurement: 4-6. Linear oxidation 4-7 Trench Filling 4-8 CMP Chapter 5 The study for Retention Time of Dynamic Access Memory (DRAM) with Shallow Trench Isolation (STI) 5-1. Introduction 5-2: Experimental 5-3 Theoretical 5-3-A Diffusion Current 5-3-B Generation-Recombination Current 5-3-C Thermionic Field Emission (TFE) Current 5-4 Results and Discussion 5-4-1 Inspection 5-4-2 Electrical characteristics 5-4-3 Retention time 5-4-4 Discussion 5-5 Conclusion Chapter 6 Formation low Temperature Epitaxial TiSi2 Silicide by Rapid Thermal Process System:Application as a Contact Metal 6-1 Introduction 6-2Experimental 6-3 Results and discussion: 6-3-1 TiSi2 epitaxial silicide 6-4 conclusion Chapter 7 Conclusion and Future work 7-1 Contributions of this study 7-2 Suggestions for future work