標題: | Using knowledge-based techniques on loop parallelization for parallelizing compilers |
作者: | Yang, CT Tseng, SS Chuang, CD Shih, WC 資訊工程學系 Department of Computer Science |
關鍵字: | parallelizing compiler;data dependence testing;loop parallelization;parallel loop scheduling;knowledge-based;repertory grid analysis;speedup |
公開日期: | 1-五月-1997 |
摘要: | In this paper we propose a knowledge-based approach for solving data dependence testing and loop scheduling problems. A rule-based system, called the K-Test, is developed by repertory grid and attribute ording table to construct the knowledge base. The K-Test chooses an appropriate testing algorithm according to some features of the input program by using knowledge-based techniques, and then applies the resulting test to detect data dependences for loop parallelization. Another rule-based system, called the KPLS, is also proposed to be able to choose an appropriate scheduling by inferring some features of loops and assign parallel loops on multiprocessors for achieving high speedup. The experimental results show that the graceful speedup obtained by our compiler is obvious. |
URI: | http://hdl.handle.net/11536/587 |
ISSN: | 0167-8191 |
期刊: | PARALLEL COMPUTING |
Volume: | 23 |
Issue: | 3 |
起始頁: | 291 |
結束頁: | 309 |
顯示於類別: | 期刊論文 |