標題: | An intelligent parallel loop scheduling for parallelizing compilers |
作者: | Fann, YW Yang, CT Tseng, SS Tsai, CJ 資訊工程學系 Department of Computer Science |
關鍵字: | parallelizing compiler;parallel loop scheduling;knowledge-based system;multiprocessor systems;speedup |
公開日期: | 1-三月-2000 |
摘要: | In this paper we propose a knowledge-based approach to solving loop-scheduling problems. A rule-based system, called IPLS, is developed by combining a repertory grid and an attribute ordering table to construct a knowledge base. IPLS chooses an appropriate scheduling algorithm by inferring some features of loops and assigning parallel loops to multiprocessors to achieve significant speedup. Because more attributes are proposed, the accuracy of selection of an appropriate scheduling method is improved. In addition, the refined IPLS system can automatically adjust the attributes in the knowledge base according to profile information; therefore, IPLS has the capability of feedback learning. The experimental results show that our approach can achieve greater speedup on multiprocessor systems than can others. |
URI: | http://hdl.handle.net/11536/30691 |
ISSN: | 1016-2364 |
期刊: | JOURNAL OF INFORMATION SCIENCE AND ENGINEERING |
Volume: | 16 |
Issue: | 2 |
起始頁: | 169 |
結束頁: | 200 |
顯示於類別: | 期刊論文 |