具分支預測功能X86超純量處理器內指令貯列之設計

Abstract

本論文提出一個新的指令貯列的設計，可應用在具有分支預測邏輯的 X86 超純量處理器環境下。一般而言，分支指令是造成系統效能不彰的主要原 因，除了因為分支指令預測失敗外尚有一原因，就是如果分支指令預測發 生跳躍會導致指令貯列被清除，而系統將會命令記憶體管理單元重新擷取 目的指令，此時會花費一個週期時間去擷取目的指令。本論文所提之設計 便是當預測分支指令發生跳躍時，系統會去檢查看看指令貯列內是否含有 所需的目的指令，如果是則不清除指令貯列，直接由指令貯列傳該指令給 解碼器。否則清除之，然後發命令給記憶體管理單元重新擷取目的指令。 當系統發現指令貯列內含有目的指令時，便可節省一個週期時間。另外本 論文中也針對幾種會影響指令貯列效能的因素做一詳盡的探討，並提出一 些檢討與改進。 In this thesis, we propose a new instruction queue design for X86 superscalar processor with branch prediction logic. The branch cause is traditionally the main instriction to abstruct the system performance. Besides the penality of branch prediction miss, a predicted taken branch instruction will cause queue to be flushed, and one cycle penality must be added to fetch the next instruction from the cache. In our design, when the branch instruction is predicted to be taken, system checks whether the target instruction is in the instruction queue. If the target instruction is indeed in the instruction queue, it is sent to the decoder directly; otherwise the instruction queue is flushed and target instruction is fetched from the code cache. This saves one cycle when the target instruction in the instruction queue. Moreover, we discuss serveral factors that affect the performance of the instruction queue, and make some suggestions for improvemest.