為多引線處理機架構設計之整合模擬評估環境之研製

Abstract

本論文中,主要探討的對象是,平行多引線單處理機,平行多引線處理機的 特色在於允許多條引線能並行的執行,共享硬體資源,如此可增加資源的使 用率以及隱藏記憶體的延遲.我們的平行多引線架構,不僅擁有平行多引線 的特性,還有超純量靜態發行的能力,以及同時多引線藉引線切換來引藏記 憶體延遲的特色.我們設計了一模擬系統不但可模擬平行多引線處理機,而 且可模擬 RISC,超純量,同時多引線幾種不同架構的處理機.我們主要利用 此模擬系統,對平行多引線處理機的效能及特性來做評估,包括運算單元使 用率以及記憶體延遲隱藏等.並評估了幾種不同架構的效能及特性.所得之 結果可供未來設計時之參考.另外,我們一方面將此一單處理機模擬系統加 以擴充為多處理機之模擬系統,一方面改寫以往發展的幾種多處理機模擬 系統,使之統一建立於 PVM 之上,以便可在多台工作站上平行執行.我們並 改進了其模擬方式,以取得較佳的模擬效能.此幫一包含 RISC,超純量,同 時多引線,平行多引線等四種 PE 架構的平行模擬與平評估環境,可提供使 用者一個多處理機整合模擬平估環境. In this thesis,we investigated the parllel multithread processor(PMP) architecture.The characteristic of parllel multithreaded processor is that multiple threads can be executed in parallel.These threads share the hardware resource thus improves the hardware utilization and hides memory access latencies.Futhermore,our parallel multithreaded processor design also provides stastic superscalar instruction issue cability and context switches between threads to hide memory access latencies.We have developed a configurable simulator that can simulate RISC,superscalar,and concurrent/ parallel multithreaded processors.With this simulator,we studied the characteristics of parallel multithreaded procesor.The evaluated design parameters include functional unit utilization and effectiveness of memory access latency hiding,etc.We collected many simulation results of different architectures to guide future system designs. Futhermore,we extend the uniprocessor simulation environment into the multiprocesso simulation environment,and adapted several existed multiprocessor simulations environment to PVM (Parallel Virtual Machine) package.We improve simulation methodology to gain simulation efficiency.As a result,we developed an integrated parallel simulation environment,which supports RISC,superscalar, concurrent/parallel multithreaded processor architectures.