標題: | 基於知識庫之平行迴圈排程 A Knowledge-Based Loop Scheduling for Parallelizing Compiler |
作者: | 莊正得 Cheng-Der Chuang 曾憲雄 Shian-Shyoung Tseng 資訊科學與工程研究所 |
關鍵字: | 平行編譯器;知識庫;迴圈平行化;平行迴圈排程;程式加速;Parallelizing compiler;knowledge-based;loop parallelization; parallel loop scheduling;speedup |
公開日期: | 1994 |
摘要: | 在本篇論文中,主要問題核心是針對平行編譯器中的平行迴圈排程加以改 進處理。有別於傳統模式,我們採用另一種思考模式來解決這個問題,即 利用知識庫來整合目前現有的迴圈排程,並擷取各種迴圈排程的優點。於 是我們提出了基於知識庫之平行迴圈排程,簡稱為KPLS,它是經由表格擷 取式的分析和屬性擇序表來架構成的專家系統。KPLS會依據所選擇迴圈的 特性加以分析後,將迴圈安排至最佳的迴圈排程方法,提高平行編譯器整 體系統效率,並改進了傳統的平行迴圈排程只能安排一種排程方法的問題 ,使得在同一個程式中的不同迴圈,能被安排不同且適用的排程方式。藉 由實驗成效可以顯示出,KPLS有良好的加速效果;另外經由知識庫的模式 ,使得系統更易於修改,同時擴增性也相對的提高了,可以知道我們的方 法優於其他的方法。 In this thesis, we concentrate on the fundamental phase, parallel loop scheduling, in parallelizing compilers. A knowledge-based approach is first proposed, which integrates existing loop scheduling algorithms to make good use of their advantages for parallelism. A rule-based system, called the knowledge-based parallel loop scheduling (KPLS), is then developed by repertory grid and attribute ordering table to construct the knowledge base. The KPLS can choose an appropriate scheduling and then apply the resulting algorithm for assigning parallel loops on multiprocessors to achieve high speedup. The experimental results show that the graceful speedup obtained by our compiler is obvious. Furthermore, as for system maintenance and extensibility, our approach is obviously superior to others. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT830394032 http://hdl.handle.net/11536/59053 |
Appears in Collections: | Thesis |