完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 龔執豪 | en_US |
dc.contributor.author | Chih-Hau Kung | en_US |
dc.contributor.author | 莊晴光 郭雙發 | en_US |
dc.contributor.author | Clive C. Tzuang and Shuang-Fa Guo | en_US |
dc.date.accessioned | 2014-12-12T02:13:40Z | - |
dc.date.available | 2014-12-12T02:13:40Z | - |
dc.date.issued | 1994 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT830430036 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/59221 | - |
dc.description.abstract | 此一設計由互補式-金屬-氧化-半導體(CMOS)電晶體構成,而電路之基本 原理係利用CMOS電晶體的平方律原則設計,共包含了乘法器電路,電壓- 電流與電流-電壓轉換電路,相位延遲電路,限制放大器電路,濾波器電 路以及數位的解調電路。 An all-CMOS FSK receiver IC has been designed and tested. It employs the square-law characteristic of CMOS transistors in saturated mode. The mixed-mode IC couples many functional blocks , a few linear voltage-to-current and current-to-voltage converters, one phase splitter for I-Q demodulation, one operational amplifier as an integrator in the phase-locked loop, a limiting amplifier before FSK signal demodulation, two cascaded sixth-order low-pass filters employing four 'Gm-C' elements, and a digital combinational logic for decoding the FSK signals coming out of the limiters in both I-Q arms. | zh_TW |
dc.language.iso | en_US | en_US |
dc.subject | 頻移; 解調; 積體電路 | zh_TW |
dc.subject | FSK; Demodulation; IC | en_US |
dc.title | 頻移鍵控解調積體電路 | zh_TW |
dc.title | Frequency Shift Keying (FSK) receiver IC | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |