利用FSK調變技術作無線通訊數據資料傳送接收器之研製

Abstract

本論文是研製一個用於數據通訊的無線傳送接收器。此傳送接收器是採用 頻移位移鍵控(Frequency shift keying)的數位調變方式。整個傳送接收 器包括電壓控制振盪器(Voltage control oscillator)、混波器(Mixer) 、鎖相迴路(Phase locked loop)電路、濾波器(F- lter)、天線切換電路 、放大器及解調器等，使本系統達到半雙工(H- alf duplex)的傳送接收 方式。在輸入端配有光耦合器(Optocoupler)，以防止PC內雜訊耦合至傳 送接收器，並且系統頻率的穩定性是由IC穩壓器(Voltage regula- tor) ，鎖相迴路及各元件的參數值控制。至於散熱問題本系統亦有考慮。由於 受限於41.3MHz FSK 訊號產生器中變容二極體(SVC321)及51 KΩ電阻的充 放電作用，所以FSK 調變速率的極限是14.4Kbps。此系統混波器是一個主 動雙平衡式混波器，約有8dB 的增益，雜訊指數(No- ise figure)為15dB 。VCO 用鎖相迴路以達到穩定輸出頻率，其可調頻率範圍為404∼414MHz 。FSK解調器的靈敏度在 -87dBm∼-27dBm，因此為了提高CNR，必須設計 雜訊指數(NF)較低的放大器以降低雜訊量對解調器的影響。在有衰落( Fading)通道的情況下，只要CNR在45dB以上，則位元差錯率(Bit error rate)可在10-8以下，因此本系統有良好的傳輸性能。 A wireless transceiver applied to data communication system has been fabricated.The transceiver consists of voltage cont- rol oscillator,mixer,phase locked loop(PLL)circuit,filter,an- tenna swith circuit,amplifier and modulator.The connection of the communication terminals is half-duplx. The phase locked loop( PLL) circuit is designed to lock the local frequency achieving the effect of high frequency stabi- lity and offers a tuning range from 404 to 414MHz.The maximum FSK modulation rate is about 14.4kbps,which is limited by the RC components in the charing path.Furthermore,the optocoupler is used in the inputs for preventing PC noise coupled the tra- nsceiver. The CNR of receiver is enhanced about 8dB by using the active double balanced mixer with 8dB gain and 15dB noise figure.The low noise amplifiers are designed to reduce the influence of noise and provid the signal level within the dynamic of FSK de- modulator(-87∼-27dBm). In fading channel,the bit error rate is below 10-8 with CNR in antenna port is above 45dB. It is concluded that the transceiver is performed in a satisfactory manner.