CMP平坦化製程對元件特性之效應

Abstract

近來化學機械研磨平坦化製程應用於多層金屬結構的表面平坦化上漸漸重 要，但是許多寄生的效應尚待探討。在本論文中，我們研究了化學機械研 磨對於位在底層的閘極氧化層的電性及可靠性的影響。由實驗結果可知， 對於化學機械研磨造成的缺陷可由適當選擇研磨壓力及時間來改善。另外 我們也應用了化學機械研磨改善複晶矽氧化層及複晶矽薄膜電晶體的特性 。結果如所預期，複晶矽氧化層的氧化層╱複晶矽介面平坦化可使得介面 位障提高，進而使漏電流減少，而元件的崩潰電壓也可以提高。此外，複 晶矽薄膜電晶體的載子移動率在介面平坦化後可提升為２倍，其他的電特 性也有改善。但是由於化學機械研磨會導致缺陷的產生，進而使改善幅度 並不很大，因此研究如何減少研磨製程的缺陷將是化學機械研磨技術的重 要課題。 CMP planarization process is more and more important on multilevel structure for resent years. In this thesis, we investigated the effects of CMP on the underlying dielectric films reliability by studing of some basic electrical characteristics. Also, directly applied CMP to improve the surface roughness of devices and thus upgrade the devices were investigated by polyoxide capacitors and top gate TFTs. In polyoxide, the results showed an improvement in suppressing leakage current and increasing breakdown field. In TFTs, the mobility of device with smooth surface also could be increased by 2 times than that with rough surface. The defects resulted from CMP process have been confirmed, and could be suppressed by choosing an appropriate polishing condition.