標題: 利用超真空化學氣相沉積成長複晶矽薄膜電晶體特性之研究
A Study of Polycrystalline Silicon Thin-Film Transistors Fabricated by Ultra-High Vacuum/ Chemical Vapor Deposition
作者: 胡志昌
Jyh-Chang Hwu
張俊彥
Dr.Chun-Yen Chang
電子研究所
關鍵字: 超真空化學氣相沉積;薄膜電晶體;化學機械研磨.;Ultra-High Vacuum/Chemical Vapor Deposition; Chemically and Mechanically polished.
公開日期: 1994
摘要: 在本論文中,我們成功地利用超真空化學氣相沉積系統製造出高性能的上 閘極及下閘極複晶矽薄膜電體.並和傳統低壓化學氣相沉積所製成的元件 比較, 前者製成的電晶體在電性上比後者好很多, 它擁有高的場效載子遷 移率和開/ 關電流比, 及低的臨界電壓和閘極波動率( 氫化後可小於250 mV/dec), 它的活化能隨閘極電壓的增加而下降很快, 這些是因為用超真 空化學氣相沉積的複晶矽薄膜界面中擁有很小的缺陷密度所致. 在此實驗 中我們使用化學機械研磨(CMP) 來改善上閘極電晶體的閘極氧化層和複晶 矽薄膜界面的平坦度, 同時氫化及複晶矽薄膜厚度對電晶體電性的影響也 加以探討. In this research,high performance bottom-gate and top- gate poly-Si TFTs with active layer grown by ultra-high vacuum /chemical vapor deposition (UHV/CVD) system have been success- fully fabricated, and firstly compared its electrical character- istics with those of devives with films grown by conventional low pressure/chemical vapor deposition (LPCVD) system. Of these two devices the former exhibits consistently a superior performance. It owns high field-effect mobility, high ON/OFF current ratio, low threshold voltage and low subthreshold swing (< 250mV/dec after hydrogenation), and its activation energy decreases very fast with the gate voltage. The improve- ment was attributed to very less trap-state density in the UHV /CVD-processed poly-Si films grain boundary. In order to get more smooth the oxide-semiconductor interface of the top-gate TFTs,the surface of the poly-Si films were chemically and mechanically polished (CMP) before oxidation, In the same time ,the effects of hydrogenation passivation and poly-Si film thickness on the performance were studied also.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT830430067
http://hdl.handle.net/11536/59256
顯示於類別:畢業論文