互補式金氧半電容耦合型靜電放電保護電路之分析及設計

Abstract

在本篇論文裡提出一個以電容耦合技術做的靜電放電保護電路。在本電路 中的電容耦合作用是藉由耦合一些暫態電壓到靜電放電防護元件的閘極上 ，此閘極電壓不僅降低靜電放電保護金氧半場效電晶體之迴轉觸發電壓， 且能卻保其均勻導通來旁通靜電放電的電流。特別是在次微米互補式金氧 半技術中，電容耦合型靜電放電保護電路可有效地保護輸入閘之薄氧化層 。另一方面，電容耦合型靜電放電保護電路亦可提升其靜電放電之損壞臨 界電壓。藉著在 3.3伏特0.5μm之靜態隨機存取記憶體的互補式金氧半技 術中之 SPICE模擬及實驗結果，本論文中亦推導出一個簡單且準確的時序 模式來設計此電容耦合型靜電放電保護電路。在不同設計參數下的靜電放 電實驗測式結果及損壞分析亦被測式且分析。針對電容耦合型靜電放電保 護電路的設計，模式計算和實驗結果顯示出極佳的吻合性。最後，則探討 一個擁有多電源供應腳的互補式金氧半積體電路之全晶片性靜電放電保護 的個案。 An electrostatic discharging (ESD) protection circuit using the capacitor-coupled technique is proposed in this thesis. In protection circuit, the capacitor-coupled technique is utlized not only to lower the snapback-trigger voltage but to ensure homogenoues current flow in the ESD protection MOSFET. Thus the thinner gate oxide of the input MOSFETs in submicron CMOS tech- nology can be effectively protected. On the other hand, the ESD failure threshold can also be increased. A simple and accurate design model for the capacitor-coupled ESD protection circuit has been derived from physical timing analysis and verified by both SPICE simulation and experimental results in 3.3-V 0.5-μm SRAM CMOS technology. The ESD testing results and failure behavior under different design parameters have also been measured and analyzed. Both model calculations and experimental results have shown a good consistence on various performance measures of the capacitor-coupled ESD protection circuit. Finally, a case study of whole-chip ESD protection for CMOS chips with multiple power supply pins has been investigated.