對以細胞單元為基礎的互補式金氧半電晶體組合電路的功率特徵化分析及功率估測

Abstract

在此篇論文中,我們對細胞單元的功率消耗提出了一種自動功率特徵化系 統,在這個自動功率特徵化系統中,輸入延遲,輸出負載,電容連結效應 ,以 及邏輯狀態圖中各狀態點間的相依性都被考慮。一個細胞單元的功率消耗 主要分為動態功率消耗,短路電路消耗,以及電容連結功率消耗三部份 ,這 三部份都將分別被討論。功率特徵化系統將應用在參考論文7的"以細胞單 元為基礎的功率估測系統"(CBPE),這個系統考慮了輸出負載電容,內部電 容以及連結電容的充放電效應。除此之外,我們也增加了CBPE在複雜邏輯 閘的應用。依照我們對一些標準線路所作的實驗結果，CBPE 比 SPICE 在 計算功率花的中央處理單元的時間上快了兩個次方以上，並且平均誤差 在11﹪左右。 In the thesis, we build an automatic power characterization system for characterizingthe power consumption behavior of each cell in cell library. In the characterization, input slew rate, output capacitance loading, capacitive feedthrough effect and the logic state dependence of nodes in a cell are taken into account. Power consumption of a cell is mainly divided into three parts, dynamic power, short circuit power, and capacitive feedthrough power. The three parts are characterized individually. Characterization results are applied to a Cell- Based Power Estimation (CBPE) system [7] which proposed a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrough effect. In addition, we also augment the CBPE system to model the estimation of complex gates. For a set of benchmark circuits, experimental results show that the accuracy of the power dissipation estimated by CBPE is on average error within 11% as compared to the exact SPICE simulation while the CPU time is more than two order of magnitudes less.