標題: | CB-power: A hierarchical power analysis and characterization environment of cell-based CMOS circuits |
作者: | Shen, WZ Lin, JY Lu, JM 交大名義發表 電子工程學系及電子研究所 National Chiao Tung University Department of Electronics Engineering and Institute of Electronics |
關鍵字: | hierarchical cell-based power estimation;power characterization;power modeling;gate-level power analysis environment |
公開日期: | 1-十月-1997 |
摘要: | In this paper, we present CB-Porver, a hierarchical power analysis and characterization environment of cell-based CMOS circuits. The environment includes two parts, a cell characterization system for timing, input capacitance as well as power and a cell-based power estimation system. The characterization system can characterize basic, complex and transmission gates. During the characterization, input slew rate, output loading, capacitive feedthrough effect and the logic state dependence of nodes in a cell are all taken into account. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power. short-circuit power and dynamic power. With the characterization data, a cell-based power estimator (CBPE) embedded in Verilog-XL is used for estimating the power consumption of the gates in a circuit. CBPE is also a hierarchical power estimator. Macrocells such as flip-flops and adders are partitioned into primitive gates during power estimation. Experimental results on a set of MCNC benchmark circuits show that the power estimation based on our power modeling and characterization provides within 6% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less. |
URI: | http://hdl.handle.net/11536/288 |
ISSN: | 0916-8508 |
期刊: | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Volume: | E80A |
Issue: | 10 |
起始頁: | 1908 |
結束頁: | 1914 |
顯示於類別: | 會議論文 |